Move the SuperIO stuff into its own files
This commit is contained in:
Vincent Barrilliot
parent
10cc43fb09
commit
d18cbd8849
12
src/Makefile
12
src/Makefile
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@ -78,7 +78,7 @@ endif
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# VERBOSE 5 Log a truly verbose message... the sort you almost never want to bother with
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# Log message above DEFAULT_LOG_LEVEL level will not even be compiled,
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# ie they will have NO chance of being output even if log_level is high enough.
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DEFAULT_LOG_LEVEL=0
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DEFAULT_LOG_LEVEL=1
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# Common defines and includes -------------------------------------------------
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@ -151,8 +151,6 @@ else
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endif
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# Define OS-dependent tools ---------------------------------------------------
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ifeq ("$(PAD_FLASH_SIZE)","")
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# When compiling an image for flash, size to which the image must be padded
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@ -166,6 +164,7 @@ else
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PAD_CMD = truncate -s $(PAD_FLASH_SIZE) $@
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endif
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# Flags (are automatically used by make) --------------------------------------
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ASFLAGS := $(ASFLAGS) $(DEFINES) $(INCLUDES)
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CFLAGS := $(CFLAGS) $(DEFINES) $(INCLUDES)
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LDFLAGS := $(LDFLAGS) $(LDFLAGS_FOR_UNIT)
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@ -188,11 +187,11 @@ cpu_c_obj := $(subst .c,.o,$(cpu_c_src)) $(subst .s,.o,$(cpu_s_src))
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dev_c_src = block.c channel.c console.c fsys.c pata.c ps2.c rtc.c sdc.c txt_screen.c uart.c
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dev_s_src =
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ifeq ($(UNIT),a2560k)
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dev_c_src := $(dev_c_src) fdc.c kbd_mo.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c m68040/fdc_m68040.c
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dev_c_src := $(dev_c_src) fdc.c kbd_mo.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c m68040/fdc_m68040.c superio.c
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else ifeq ($(UNIT),genx)
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dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c
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dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c superio.c
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else ifeq ($(UNIT),a2560x)
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dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c
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dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c superio.c
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else ifeq ($(UNIT),a2560u)
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dev_c_src := $(dev_c_src) txt_a2560u.o
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endif
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@ -249,6 +248,7 @@ foenixmcp.s68: $(DEPS)
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foenixmcp.bin: $(DEPS)
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$(CC) $(LDFLAGS) -o $@ $(FILES_TO_LINK)
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# TODO Test that the file is <= PAD_FLASH_SIZE bytes otherwise'll be slashing the OS !
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$(PAD_CMD)
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# Rule for generating include file containing RLE-compressed version of BMP splashscreen
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232
src/dev/superio.c
Normal file
232
src/dev/superio.c
Normal file
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@ -0,0 +1,232 @@
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/* Functions for the SuperIO */
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#include "superio.h"
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#if HAS_SUPERIO
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static void init_SuperIO_config_zones(void);
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/*
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* Initialize the SuperIO registers
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*/
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void init_superio(void) {
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init_SuperIO_config_zones(); // This Init used to be done by the FPGA.
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*GP10_REG = 0x01;
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*GP11_REG = 0x01;
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*GP12_REG = 0x01;
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*GP13_REG = 0x01;
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*GP14_REG = 0x05;
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*GP15_REG = 0x05;
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*GP16_REG = 0x05;
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*GP17_REG = 0x05;
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*GP20_REG = 0x00;
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*GP24_REG = 0x01;
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*GP25_REG = 0x05;
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*GP26_REG = 0x84;
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*GP30_REG = 0x01;
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*GP31_REG = 0x01;
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*GP32_REG = 0x01;
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*GP33_REG = 0x04; // FAN1 GPIO Config
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*GP34_REG = 0x01;
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*GP35_REG = 0x01;
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*GP36_REG = 0x01;
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*GP37_REG = 0x01;
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*GP42_REG = 0x01;
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*GP43_REG = 0x01;
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*GP50_REG = 0x05;
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*GP51_REG = 0x05;
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*GP52_REG = 0x05;
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*GP53_REG = 0x04;
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*GP54_REG = 0x05;
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*GP55_REG = 0x04;
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*GP56_REG = 0x05;
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*GP57_REG = 0x04;
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*GP60_REG = 0x84;
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*GP61_REG = 0x84;
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*GP1_REG = 0x00;
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*GP2_REG = 0x01;
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*GP3_REG = 0x00;
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*GP4_REG = 0x00;
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*GP5_REG = 0x00;
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*GP6_REG = 0x00;
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*LED1_REG = 0x01;
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*LED2_REG = 0x02;
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*FAN1_REG = 0xE0; // <= Value to change to Get the Fan running.
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// See doc for more options, need to set $80 to get it started and use other bits to change the PWN...
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*FAN_CTRL_REG = 0x01;
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}
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static void init_SuperIO_config_zones(void) {
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// First step is to get into the Configuration Mode
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*CONFIG_0x2E_REG = 0x55; // We need to Get into the Config Mode with 0x55
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// Setting Up Device 0 - Floppy
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// {8'h06,16'h03F0,8'h00};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x00;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x03;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0xF0;
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// INT
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x06;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 3 - Parallel Port
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// {8'h07,16'h0378,8'h03};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x03;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x03;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0x78;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x07;
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// Parallel Mode
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*CONFIG_0x2E_REG = 0xF0;
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*CONFIG_0x2F_REG = 0x3A;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 4 - Serial Port 1
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// {8'h04,16'h03F8,8'h04};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x04;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x03;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0xF8;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x04;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 5 - Serial Port 2
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// {8'h03,16'h02F8,8'h05};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x05;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x02;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0xF8;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x03;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 7 - Keyboard
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// {8'h01, 16'h0060,8'h07};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x07;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x00;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0x60;
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// INT0 (Keyboard)
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x01;
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// INT1 (mouse)
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*CONFIG_0x2E_REG = 0x72;
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*CONFIG_0x2F_REG = 0x02;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 9 - Game Port
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// {8'h00, 16'h0200,8'h09};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x09;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x02;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0x00;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x00;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 10 - PME (Power Management)
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// {8'h00, 16'h0100,8'h0A};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x0A;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x01;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0x00;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x00;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Setting Up Device 11 - PME (Power Management)
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// {8'h05,16'h0330,8'h0B};
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// LD
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*CONFIG_0x2E_REG = 0x07;
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*CONFIG_0x2F_REG = 0x0B;
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// BA_H (Base address)
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*CONFIG_0x2E_REG = 0x60;
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*CONFIG_0x2F_REG = 0x03;
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// BA_L
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*CONFIG_0x2E_REG = 0x61;
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*CONFIG_0x2F_REG = 0x30;
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// INT0
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*CONFIG_0x2E_REG = 0x70;
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*CONFIG_0x2F_REG = 0x05;
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// Enable the Zone
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*CONFIG_0x2E_REG = 0x30;
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*CONFIG_0x2F_REG = 0x01;
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// Supplemental Settings
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// Power On Device
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*CONFIG_0x2E_REG = 0x22;
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*CONFIG_0x2F_REG = 0xFF;
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// We are done with config.
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*CONFIG_0x2E_REG = 0xAA; // We need to Get into the Config Mode with 0x55
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*GP60_REG = 0x84; // THis is to replicate the FPGA behavior when it did the config.
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*LED1_REG = 0x01; // THis is to replace the FPGA behavior when it did the config in hardware.
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}
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#endif
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@ -9,105 +9,110 @@
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#ifndef __SUPERIO_H
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#define __SUPERIO_H
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#define CONFIG_0x2E_REG ((volatile unsigned char *)0xFEC0202E)
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#define CONFIG_0x2F_REG ((volatile unsigned char *)0xFEC0202F)
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#include <stdint.h>
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#define PME_STS_REG ((volatile unsigned char *)0xFEC02100)
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#define PME_EN_REG ((volatile unsigned char *)0xFEC02102)
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#define SUPERIO_BASE (0xFEC02000)
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#define PME_STS1_REG ((volatile unsigned char *)0xFEC02104)
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#define PME_STS2_REG ((volatile unsigned char *)0xFEC02105)
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#define PME_STS3_REG ((volatile unsigned char *)0xFEC02106)
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#define PME_STS4_REG ((volatile unsigned char *)0xFEC02107)
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#define PME_STS5_REG ((volatile unsigned char *)0xFEC02108)
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#define PME_EN1_REG ((volatile unsigned char *)0xFEC0210A)
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#define PME_EN2_REG ((volatile unsigned char *)0xFEC0210B)
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#define PME_EN3_REG ((volatile unsigned char *)0xFEC0210C)
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#define PME_EN4_REG ((volatile unsigned char *)0xFEC0210D)
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#define PME_EN5_REG ((volatile unsigned char *)0xFEC0210E)
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#define CONFIG_0x2E_REG ((volatile uint8_t *)0xFEC0202E)
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#define CONFIG_0x2F_REG ((volatile uint8_t *)0xFEC0202F)
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#define SMI_STS1_REG ((volatile unsigned char *)0xFEC02110)
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#define SMI_STS2_REG ((volatile unsigned char *)0xFEC02111)
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#define SMI_STS3_REG ((volatile unsigned char *)0xFEC02112)
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#define SMI_STS4_REG ((volatile unsigned char *)0xFEC02113)
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#define SMI_STS5_REG ((volatile unsigned char *)0xFEC02114)
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#define PME_STS_REG ((volatile uint8_t *)0xFEC02100)
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#define PME_EN_REG ((volatile uint8_t *)0xFEC02102)
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#define SMI_EN1_REG ((volatile unsigned char *)0xFEC02116)
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#define SMI_EN2_REG ((volatile unsigned char *)0xFEC02117)
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#define SMI_EN3_REG ((volatile unsigned char *)0xFEC02118)
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#define SMI_EN4_REG ((volatile unsigned char *)0xFEC02119)
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#define SMI_EN5_REG ((volatile unsigned char *)0xFEC0211A)
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#define PME_STS1_REG ((volatile uint8_t *)0xFEC02104)
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#define PME_STS2_REG ((volatile uint8_t *)0xFEC02105)
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#define PME_STS3_REG ((volatile uint8_t *)0xFEC02106)
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#define PME_STS4_REG ((volatile uint8_t *)0xFEC02107)
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#define PME_STS5_REG ((volatile uint8_t *)0xFEC02108)
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#define MSC_ST_REG ((volatile unsigned char *)0xFEC0211C)
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#define FORCE_DISK_CHANGE ((volatile unsigned char *)0xFEC0211E)
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#define FLOPPY_DATA_RATE ((volatile unsigned char *)0xFEC0211F)
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#define PME_EN1_REG ((volatile uint8_t *)0xFEC0210A)
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#define PME_EN2_REG ((volatile uint8_t *)0xFEC0210B)
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#define PME_EN3_REG ((volatile uint8_t *)0xFEC0210C)
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#define PME_EN4_REG ((volatile uint8_t *)0xFEC0210D)
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#define PME_EN5_REG ((volatile uint8_t *)0xFEC0210E)
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#define UART1_FIFO_CTRL_SHDW ((volatile unsigned char *)0xFEC02120)
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#define UART2_FIFO_CTRL_SHDW ((volatile unsigned char *)0xFEC02121)
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#define DEV_DISABLE_REG ((volatile unsigned char *)0xFEC02122)
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#define SMI_STS1_REG ((volatile uint8_t *)0xFEC02110)
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#define SMI_STS2_REG ((volatile uint8_t *)0xFEC02111)
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#define SMI_STS3_REG ((volatile uint8_t *)0xFEC02112)
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#define SMI_STS4_REG ((volatile uint8_t *)0xFEC02113)
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#define SMI_STS5_REG ((volatile uint8_t *)0xFEC02114)
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#define GP10_REG ((volatile unsigned char *)0xFEC02123)
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#define GP11_REG ((volatile unsigned char *)0xFEC02124)
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#define GP12_REG ((volatile unsigned char *)0xFEC02125)
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#define GP13_REG ((volatile unsigned char *)0xFEC02126)
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#define GP14_REG ((volatile unsigned char *)0xFEC02127)
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#define GP15_REG ((volatile unsigned char *)0xFEC02128)
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#define GP16_REG ((volatile unsigned char *)0xFEC02129)
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#define GP17_REG ((volatile unsigned char *)0xFEC0212A)
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#define SMI_EN1_REG ((volatile uint8_t *)0xFEC02116)
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#define SMI_EN2_REG ((volatile uint8_t *)0xFEC02117)
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#define SMI_EN3_REG ((volatile uint8_t *)0xFEC02118)
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#define SMI_EN4_REG ((volatile uint8_t *)0xFEC02119)
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#define SMI_EN5_REG ((volatile uint8_t *)0xFEC0211A)
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#define GP20_REG ((volatile unsigned char *)0xFEC0212B)
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#define GP21_REG ((volatile unsigned char *)0xFEC0212C)
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#define GP22_REG ((volatile unsigned char *)0xFEC0212D)
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#define GP23_REG ((volatile unsigned char *)0xFEC0212E)
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#define GP24_REG ((volatile unsigned char *)0xFEC0212F)
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#define GP25_REG ((volatile unsigned char *)0xFEC02130)
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#define GP26_REG ((volatile unsigned char *)0xFEC02131)
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#define GP27_REG ((volatile unsigned char *)0xFEC02132)
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#define MSC_ST_REG ((volatile uint8_t *)0xFEC0211C)
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#define FORCE_DISK_CHANGE ((volatile uint8_t *)0xFEC0211E)
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#define FLOPPY_DATA_RATE ((volatile uint8_t *)0xFEC0211F)
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#define GP30_REG ((volatile unsigned char *)0xFEC02133)
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#define GP31_REG ((volatile unsigned char *)0xFEC02134)
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#define GP32_REG ((volatile unsigned char *)0xFEC02135)
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||||
#define GP33_REG ((volatile unsigned char *)0xFEC02136)
|
||||
#define GP34_REG ((volatile unsigned char *)0xFEC02137)
|
||||
#define GP35_REG ((volatile unsigned char *)0xFEC02138)
|
||||
#define GP36_REG ((volatile unsigned char *)0xFEC02139)
|
||||
#define GP37_REG ((volatile unsigned char *)0xFEC0213A)
|
||||
#define UART1_FIFO_CTRL_SHDW ((volatile uint8_t *)0xFEC02120)
|
||||
#define UART2_FIFO_CTRL_SHDW ((volatile uint8_t *)0xFEC02121)
|
||||
#define DEV_DISABLE_REG ((volatile uint8_t *)0xFEC02122)
|
||||
|
||||
#define GP40_REG ((volatile unsigned char *)0xFEC0213B)
|
||||
#define GP41_REG ((volatile unsigned char *)0xFEC0213C)
|
||||
#define GP42_REG ((volatile unsigned char *)0xFEC0213D)
|
||||
#define GP43_REG ((volatile unsigned char *)0xFEC0213E)
|
||||
#define GP10_REG ((volatile uint8_t *)0xFEC02123)
|
||||
#define GP11_REG ((volatile uint8_t *)0xFEC02124)
|
||||
#define GP12_REG ((volatile uint8_t *)0xFEC02125)
|
||||
#define GP13_REG ((volatile uint8_t *)0xFEC02126)
|
||||
#define GP14_REG ((volatile uint8_t *)0xFEC02127)
|
||||
#define GP15_REG ((volatile uint8_t *)0xFEC02128)
|
||||
#define GP16_REG ((volatile uint8_t *)0xFEC02129)
|
||||
#define GP17_REG ((volatile uint8_t *)0xFEC0212A)
|
||||
|
||||
#define GP50_REG ((volatile unsigned char *)0xFEC0213F)
|
||||
#define GP51_REG ((volatile unsigned char *)0xFEC02140)
|
||||
#define GP52_REG ((volatile unsigned char *)0xFEC02141)
|
||||
#define GP53_REG ((volatile unsigned char *)0xFEC02142)
|
||||
#define GP54_REG ((volatile unsigned char *)0xFEC02143)
|
||||
#define GP55_REG ((volatile unsigned char *)0xFEC02144)
|
||||
#define GP56_REG ((volatile unsigned char *)0xFEC02145)
|
||||
#define GP57_REG ((volatile unsigned char *)0xFEC02146)
|
||||
#define GP20_REG ((volatile uint8_t *)0xFEC0212B)
|
||||
#define GP21_REG ((volatile uint8_t *)0xFEC0212C)
|
||||
#define GP22_REG ((volatile uint8_t *)0xFEC0212D)
|
||||
#define GP23_REG ((volatile uint8_t *)0xFEC0212E)
|
||||
#define GP24_REG ((volatile uint8_t *)0xFEC0212F)
|
||||
#define GP25_REG ((volatile uint8_t *)0xFEC02130)
|
||||
#define GP26_REG ((volatile uint8_t *)0xFEC02131)
|
||||
#define GP27_REG ((volatile uint8_t *)0xFEC02132)
|
||||
|
||||
#define GP60_REG ((volatile unsigned char *)0xFEC02147)
|
||||
#define GP61_REG ((volatile unsigned char *)0xFEC02148)
|
||||
#define GP30_REG ((volatile uint8_t *)0xFEC02133)
|
||||
#define GP31_REG ((volatile uint8_t *)0xFEC02134)
|
||||
#define GP32_REG ((volatile uint8_t *)0xFEC02135)
|
||||
#define GP33_REG ((volatile uint8_t *)0xFEC02136)
|
||||
#define GP34_REG ((volatile uint8_t *)0xFEC02137)
|
||||
#define GP35_REG ((volatile uint8_t *)0xFEC02138)
|
||||
#define GP36_REG ((volatile uint8_t *)0xFEC02139)
|
||||
#define GP37_REG ((volatile uint8_t *)0xFEC0213A)
|
||||
|
||||
#define GP1_REG ((volatile unsigned char *)0xFEC0214B)
|
||||
#define GP2_REG ((volatile unsigned char *)0xFEC0214C)
|
||||
#define GP3_REG ((volatile unsigned char *)0xFEC0214D)
|
||||
#define GP4_REG ((volatile unsigned char *)0xFEC0214E)
|
||||
#define GP5_REG ((volatile unsigned char *)0xFEC0214F)
|
||||
#define GP6_REG ((volatile unsigned char *)0xFEC02150)
|
||||
#define GP40_REG ((volatile uint8_t *)0xFEC0213B)
|
||||
#define GP41_REG ((volatile uint8_t *)0xFEC0213C)
|
||||
#define GP42_REG ((volatile uint8_t *)0xFEC0213D)
|
||||
#define GP43_REG ((volatile uint8_t *)0xFEC0213E)
|
||||
|
||||
#define FAN1_REG ((volatile unsigned char *)0xFEC02156)
|
||||
#define FAN2_REG ((volatile unsigned char *)0xFEC02157)
|
||||
#define FAN_CTRL_REG ((volatile unsigned char *)0xFEC02158)
|
||||
#define FAN1_TACH_REG ((volatile unsigned char *)0xFEC02159)
|
||||
#define FAN2_TACH_REG ((volatile unsigned char *)0xFEC0215A)
|
||||
#define FAN1_PRELOAD_REG ((volatile unsigned char *)0xFEC0215B)
|
||||
#define FAN2_PRELOAD_REG ((volatile unsigned char *)0xFEC0215C)
|
||||
#define GP50_REG ((volatile uint8_t *)0xFEC0213F)
|
||||
#define GP51_REG ((volatile uint8_t *)0xFEC02140)
|
||||
#define GP52_REG ((volatile uint8_t *)0xFEC02141)
|
||||
#define GP53_REG ((volatile uint8_t *)0xFEC02142)
|
||||
#define GP54_REG ((volatile uint8_t *)0xFEC02143)
|
||||
#define GP55_REG ((volatile uint8_t *)0xFEC02144)
|
||||
#define GP56_REG ((volatile uint8_t *)0xFEC02145)
|
||||
#define GP57_REG ((volatile uint8_t *)0xFEC02146)
|
||||
|
||||
#define LED1_REG ((volatile unsigned char *)0xFEC0215D)
|
||||
#define LED2_REG ((volatile unsigned char *)0xFEC0215E)
|
||||
#define KEYBOARD_SCAN_CODE ((volatile unsigned char *)0xFEC0215F)
|
||||
#define GP60_REG ((volatile uint8_t *)0xFEC02147)
|
||||
#define GP61_REG ((volatile uint8_t *)0xFEC02148)
|
||||
|
||||
#define GP1_REG ((volatile uint8_t *)0xFEC0214B)
|
||||
#define GP2_REG ((volatile uint8_t *)0xFEC0214C)
|
||||
#define GP3_REG ((volatile uint8_t *)0xFEC0214D)
|
||||
#define GP4_REG ((volatile uint8_t *)0xFEC0214E)
|
||||
#define GP5_REG ((volatile uint8_t *)0xFEC0214F)
|
||||
#define GP6_REG ((volatile uint8_t *)0xFEC02150)
|
||||
|
||||
#define FAN1_REG ((volatile uint8_t *)0xFEC02156)
|
||||
#define FAN2_REG ((volatile uint8_t *)0xFEC02157)
|
||||
#define FAN_CTRL_REG ((volatile uint8_t *)0xFEC02158)
|
||||
#define FAN1_TACH_REG ((volatile uint8_t *)0xFEC02159)
|
||||
#define FAN2_TACH_REG ((volatile uint8_t *)0xFEC0215A)
|
||||
#define FAN1_PRELOAD_REG ((volatile uint8_t *)0xFEC0215B)
|
||||
#define FAN2_PRELOAD_REG ((volatile uint8_t *)0xFEC0215C)
|
||||
|
||||
#define LED1_REG ((volatile uint8_t *)0xFEC0215D)
|
||||
#define LED2_REG ((volatile uint8_t *)0xFEC0215E)
|
||||
#define KEYBOARD_SCAN_CODE ((volatile uint8_t *)0xFEC0215F)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue