From d18cbd88496a5446ae438294cb51635da0a3923b Mon Sep 17 00:00:00 2001 From: Vincent Barrilliot Date: Sun, 3 Dec 2023 22:24:19 +0100 Subject: [PATCH] Move the SuperIO stuff into its own files --- src/Makefile | 12 +-- src/dev/superio.c | 232 ++++++++++++++++++++++++++++++++++++++++++ src/include/superio.h | 173 ++++++++++++++++--------------- 3 files changed, 327 insertions(+), 90 deletions(-) create mode 100644 src/dev/superio.c diff --git a/src/Makefile b/src/Makefile index a2f2214..9a0d8d6 100644 --- a/src/Makefile +++ b/src/Makefile @@ -78,7 +78,7 @@ endif # VERBOSE 5 Log a truly verbose message... the sort you almost never want to bother with # Log message above DEFAULT_LOG_LEVEL level will not even be compiled, # ie they will have NO chance of being output even if log_level is high enough. -DEFAULT_LOG_LEVEL=0 +DEFAULT_LOG_LEVEL=1 # Common defines and includes ------------------------------------------------- @@ -151,8 +151,6 @@ else endif - - # Define OS-dependent tools --------------------------------------------------- ifeq ("$(PAD_FLASH_SIZE)","") # When compiling an image for flash, size to which the image must be padded @@ -166,6 +164,7 @@ else PAD_CMD = truncate -s $(PAD_FLASH_SIZE) $@ endif +# Flags (are automatically used by make) -------------------------------------- ASFLAGS := $(ASFLAGS) $(DEFINES) $(INCLUDES) CFLAGS := $(CFLAGS) $(DEFINES) $(INCLUDES) LDFLAGS := $(LDFLAGS) $(LDFLAGS_FOR_UNIT) @@ -188,11 +187,11 @@ cpu_c_obj := $(subst .c,.o,$(cpu_c_src)) $(subst .s,.o,$(cpu_s_src)) dev_c_src = block.c channel.c console.c fsys.c pata.c ps2.c rtc.c sdc.c txt_screen.c uart.c dev_s_src = ifeq ($(UNIT),a2560k) - dev_c_src := $(dev_c_src) fdc.c kbd_mo.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c m68040/fdc_m68040.c + dev_c_src := $(dev_c_src) fdc.c kbd_mo.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c m68040/fdc_m68040.c superio.c else ifeq ($(UNIT),genx) - dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c + dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c superio.c else ifeq ($(UNIT),a2560x) - dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c + dev_c_src := $(dev_c_src) fdc.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c #m68040/fdc_m68040.c superio.c else ifeq ($(UNIT),a2560u) dev_c_src := $(dev_c_src) txt_a2560u.o endif @@ -249,6 +248,7 @@ foenixmcp.s68: $(DEPS) foenixmcp.bin: $(DEPS) $(CC) $(LDFLAGS) -o $@ $(FILES_TO_LINK) +# TODO Test that the file is <= PAD_FLASH_SIZE bytes otherwise'll be slashing the OS ! $(PAD_CMD) # Rule for generating include file containing RLE-compressed version of BMP splashscreen diff --git a/src/dev/superio.c b/src/dev/superio.c new file mode 100644 index 0000000..01d9aab --- /dev/null +++ b/src/dev/superio.c @@ -0,0 +1,232 @@ +/* Functions for the SuperIO */ + +#include "superio.h" + +#if HAS_SUPERIO + +static void init_SuperIO_config_zones(void); + +/* + * Initialize the SuperIO registers + */ + void init_superio(void) { + init_SuperIO_config_zones(); // This Init used to be done by the FPGA. + + *GP10_REG = 0x01; + *GP11_REG = 0x01; + *GP12_REG = 0x01; + *GP13_REG = 0x01; + *GP14_REG = 0x05; + *GP15_REG = 0x05; + *GP16_REG = 0x05; + *GP17_REG = 0x05; + + *GP20_REG = 0x00; + *GP24_REG = 0x01; + *GP25_REG = 0x05; + *GP26_REG = 0x84; + + *GP30_REG = 0x01; + *GP31_REG = 0x01; + *GP32_REG = 0x01; + *GP33_REG = 0x04; // FAN1 GPIO Config + *GP34_REG = 0x01; + *GP35_REG = 0x01; + *GP36_REG = 0x01; + *GP37_REG = 0x01; + + *GP42_REG = 0x01; + *GP43_REG = 0x01; + + *GP50_REG = 0x05; + *GP51_REG = 0x05; + *GP52_REG = 0x05; + *GP53_REG = 0x04; + *GP54_REG = 0x05; + *GP55_REG = 0x04; + *GP56_REG = 0x05; + *GP57_REG = 0x04; + + *GP60_REG = 0x84; + *GP61_REG = 0x84; + + *GP1_REG = 0x00; + *GP2_REG = 0x01; + *GP3_REG = 0x00; + *GP4_REG = 0x00; + *GP5_REG = 0x00; + *GP6_REG = 0x00; + + *LED1_REG = 0x01; + *LED2_REG = 0x02; + + *FAN1_REG = 0xE0; // <= Value to change to Get the Fan running. + // See doc for more options, need to set $80 to get it started and use other bits to change the PWN... + *FAN_CTRL_REG = 0x01; + } + +static void init_SuperIO_config_zones(void) { + // First step is to get into the Configuration Mode + *CONFIG_0x2E_REG = 0x55; // We need to Get into the Config Mode with 0x55 + + // Setting Up Device 0 - Floppy + // {8'h06,16'h03F0,8'h00}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x00; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x03; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0xF0; + // INT + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x06; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 3 - Parallel Port + // {8'h07,16'h0378,8'h03}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x03; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x03; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0x78; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x07; + // Parallel Mode + *CONFIG_0x2E_REG = 0xF0; + *CONFIG_0x2F_REG = 0x3A; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 4 - Serial Port 1 + // {8'h04,16'h03F8,8'h04}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x04; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x03; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0xF8; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x04; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 5 - Serial Port 2 + // {8'h03,16'h02F8,8'h05}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x05; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x02; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0xF8; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x03; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 7 - Keyboard + // {8'h01, 16'h0060,8'h07}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x07; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x00; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0x60; + // INT0 (Keyboard) + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x01; + // INT1 (mouse) + *CONFIG_0x2E_REG = 0x72; + *CONFIG_0x2F_REG = 0x02; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 9 - Game Port + // {8'h00, 16'h0200,8'h09}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x09; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x02; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0x00; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x00; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 10 - PME (Power Management) + // {8'h00, 16'h0100,8'h0A}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x0A; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x01; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0x00; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x00; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Setting Up Device 11 - PME (Power Management) + // {8'h05,16'h0330,8'h0B}; + // LD + *CONFIG_0x2E_REG = 0x07; + *CONFIG_0x2F_REG = 0x0B; + // BA_H (Base address) + *CONFIG_0x2E_REG = 0x60; + *CONFIG_0x2F_REG = 0x03; + // BA_L + *CONFIG_0x2E_REG = 0x61; + *CONFIG_0x2F_REG = 0x30; + // INT0 + *CONFIG_0x2E_REG = 0x70; + *CONFIG_0x2F_REG = 0x05; + // Enable the Zone + *CONFIG_0x2E_REG = 0x30; + *CONFIG_0x2F_REG = 0x01; + + // Supplemental Settings + // Power On Device + *CONFIG_0x2E_REG = 0x22; + *CONFIG_0x2F_REG = 0xFF; + // We are done with config. + *CONFIG_0x2E_REG = 0xAA; // We need to Get into the Config Mode with 0x55 + + *GP60_REG = 0x84; // THis is to replicate the FPGA behavior when it did the config. + *LED1_REG = 0x01; // THis is to replace the FPGA behavior when it did the config in hardware. + } +#endif diff --git a/src/include/superio.h b/src/include/superio.h index 983af51..33e5958 100644 --- a/src/include/superio.h +++ b/src/include/superio.h @@ -9,105 +9,110 @@ #ifndef __SUPERIO_H #define __SUPERIO_H -#define CONFIG_0x2E_REG ((volatile unsigned char *)0xFEC0202E) -#define CONFIG_0x2F_REG ((volatile unsigned char *)0xFEC0202F) +#include -#define PME_STS_REG ((volatile unsigned char *)0xFEC02100) -#define PME_EN_REG ((volatile unsigned char *)0xFEC02102) +#define SUPERIO_BASE (0xFEC02000) -#define PME_STS1_REG ((volatile unsigned char *)0xFEC02104) -#define PME_STS2_REG ((volatile unsigned char *)0xFEC02105) -#define PME_STS3_REG ((volatile unsigned char *)0xFEC02106) -#define PME_STS4_REG ((volatile unsigned char *)0xFEC02107) -#define PME_STS5_REG ((volatile unsigned char *)0xFEC02108) -#define PME_EN1_REG ((volatile unsigned char *)0xFEC0210A) -#define PME_EN2_REG ((volatile unsigned char *)0xFEC0210B) -#define PME_EN3_REG ((volatile unsigned char *)0xFEC0210C) -#define PME_EN4_REG ((volatile unsigned char *)0xFEC0210D) -#define PME_EN5_REG ((volatile unsigned char *)0xFEC0210E) +#define CONFIG_0x2E_REG ((volatile uint8_t *)0xFEC0202E) +#define CONFIG_0x2F_REG ((volatile uint8_t *)0xFEC0202F) -#define SMI_STS1_REG ((volatile unsigned char *)0xFEC02110) -#define SMI_STS2_REG ((volatile unsigned char *)0xFEC02111) -#define SMI_STS3_REG ((volatile unsigned char *)0xFEC02112) -#define SMI_STS4_REG ((volatile unsigned char *)0xFEC02113) -#define SMI_STS5_REG ((volatile unsigned char *)0xFEC02114) +#define PME_STS_REG ((volatile uint8_t *)0xFEC02100) +#define PME_EN_REG ((volatile uint8_t *)0xFEC02102) -#define SMI_EN1_REG ((volatile unsigned char *)0xFEC02116) -#define SMI_EN2_REG ((volatile unsigned char *)0xFEC02117) -#define SMI_EN3_REG ((volatile unsigned char *)0xFEC02118) -#define SMI_EN4_REG ((volatile unsigned char *)0xFEC02119) -#define SMI_EN5_REG ((volatile unsigned char *)0xFEC0211A) +#define PME_STS1_REG ((volatile uint8_t *)0xFEC02104) +#define PME_STS2_REG ((volatile uint8_t *)0xFEC02105) +#define PME_STS3_REG ((volatile uint8_t *)0xFEC02106) +#define PME_STS4_REG ((volatile uint8_t *)0xFEC02107) +#define PME_STS5_REG ((volatile uint8_t *)0xFEC02108) -#define MSC_ST_REG ((volatile unsigned char *)0xFEC0211C) -#define FORCE_DISK_CHANGE ((volatile unsigned char *)0xFEC0211E) -#define FLOPPY_DATA_RATE ((volatile unsigned char *)0xFEC0211F) +#define PME_EN1_REG ((volatile uint8_t *)0xFEC0210A) +#define PME_EN2_REG ((volatile uint8_t *)0xFEC0210B) +#define PME_EN3_REG ((volatile uint8_t *)0xFEC0210C) +#define PME_EN4_REG ((volatile uint8_t *)0xFEC0210D) +#define PME_EN5_REG ((volatile uint8_t *)0xFEC0210E) -#define UART1_FIFO_CTRL_SHDW ((volatile unsigned char *)0xFEC02120) -#define UART2_FIFO_CTRL_SHDW ((volatile unsigned char *)0xFEC02121) -#define DEV_DISABLE_REG ((volatile unsigned char *)0xFEC02122) +#define SMI_STS1_REG ((volatile uint8_t *)0xFEC02110) +#define SMI_STS2_REG ((volatile uint8_t *)0xFEC02111) +#define SMI_STS3_REG ((volatile uint8_t *)0xFEC02112) +#define SMI_STS4_REG ((volatile uint8_t *)0xFEC02113) +#define SMI_STS5_REG ((volatile uint8_t *)0xFEC02114) -#define GP10_REG ((volatile unsigned char *)0xFEC02123) -#define GP11_REG ((volatile unsigned char *)0xFEC02124) -#define GP12_REG ((volatile unsigned char *)0xFEC02125) -#define GP13_REG ((volatile unsigned char *)0xFEC02126) -#define GP14_REG ((volatile unsigned char *)0xFEC02127) -#define GP15_REG ((volatile unsigned char *)0xFEC02128) -#define GP16_REG ((volatile unsigned char *)0xFEC02129) -#define GP17_REG ((volatile unsigned char *)0xFEC0212A) +#define SMI_EN1_REG ((volatile uint8_t *)0xFEC02116) +#define SMI_EN2_REG ((volatile uint8_t *)0xFEC02117) +#define SMI_EN3_REG ((volatile uint8_t *)0xFEC02118) +#define SMI_EN4_REG ((volatile uint8_t *)0xFEC02119) +#define SMI_EN5_REG ((volatile uint8_t *)0xFEC0211A) -#define GP20_REG ((volatile unsigned char *)0xFEC0212B) -#define GP21_REG ((volatile unsigned char *)0xFEC0212C) -#define GP22_REG ((volatile unsigned char *)0xFEC0212D) -#define GP23_REG ((volatile unsigned char *)0xFEC0212E) -#define GP24_REG ((volatile unsigned char *)0xFEC0212F) -#define GP25_REG ((volatile unsigned char *)0xFEC02130) -#define GP26_REG ((volatile unsigned char *)0xFEC02131) -#define GP27_REG ((volatile unsigned char *)0xFEC02132) +#define MSC_ST_REG ((volatile uint8_t *)0xFEC0211C) +#define FORCE_DISK_CHANGE ((volatile uint8_t *)0xFEC0211E) +#define FLOPPY_DATA_RATE ((volatile uint8_t *)0xFEC0211F) -#define GP30_REG ((volatile unsigned char *)0xFEC02133) -#define GP31_REG ((volatile unsigned char *)0xFEC02134) -#define GP32_REG ((volatile unsigned char *)0xFEC02135) -#define GP33_REG ((volatile unsigned char *)0xFEC02136) -#define GP34_REG ((volatile unsigned char *)0xFEC02137) -#define GP35_REG ((volatile unsigned char *)0xFEC02138) -#define GP36_REG ((volatile unsigned char *)0xFEC02139) -#define GP37_REG ((volatile unsigned char *)0xFEC0213A) +#define UART1_FIFO_CTRL_SHDW ((volatile uint8_t *)0xFEC02120) +#define UART2_FIFO_CTRL_SHDW ((volatile uint8_t *)0xFEC02121) +#define DEV_DISABLE_REG ((volatile uint8_t *)0xFEC02122) -#define GP40_REG ((volatile unsigned char *)0xFEC0213B) -#define GP41_REG ((volatile unsigned char *)0xFEC0213C) -#define GP42_REG ((volatile unsigned char *)0xFEC0213D) -#define GP43_REG ((volatile unsigned char *)0xFEC0213E) +#define GP10_REG ((volatile uint8_t *)0xFEC02123) +#define GP11_REG ((volatile uint8_t *)0xFEC02124) +#define GP12_REG ((volatile uint8_t *)0xFEC02125) +#define GP13_REG ((volatile uint8_t *)0xFEC02126) +#define GP14_REG ((volatile uint8_t *)0xFEC02127) +#define GP15_REG ((volatile uint8_t *)0xFEC02128) +#define GP16_REG ((volatile uint8_t *)0xFEC02129) +#define GP17_REG ((volatile uint8_t *)0xFEC0212A) -#define GP50_REG ((volatile unsigned char *)0xFEC0213F) -#define GP51_REG ((volatile unsigned char *)0xFEC02140) -#define GP52_REG ((volatile unsigned char *)0xFEC02141) -#define GP53_REG ((volatile unsigned char *)0xFEC02142) -#define GP54_REG ((volatile unsigned char *)0xFEC02143) -#define GP55_REG ((volatile unsigned char *)0xFEC02144) -#define GP56_REG ((volatile unsigned char *)0xFEC02145) -#define GP57_REG ((volatile unsigned char *)0xFEC02146) +#define GP20_REG ((volatile uint8_t *)0xFEC0212B) +#define GP21_REG ((volatile uint8_t *)0xFEC0212C) +#define GP22_REG ((volatile uint8_t *)0xFEC0212D) +#define GP23_REG ((volatile uint8_t *)0xFEC0212E) +#define GP24_REG ((volatile uint8_t *)0xFEC0212F) +#define GP25_REG ((volatile uint8_t *)0xFEC02130) +#define GP26_REG ((volatile uint8_t *)0xFEC02131) +#define GP27_REG ((volatile uint8_t *)0xFEC02132) -#define GP60_REG ((volatile unsigned char *)0xFEC02147) -#define GP61_REG ((volatile unsigned char *)0xFEC02148) +#define GP30_REG ((volatile uint8_t *)0xFEC02133) +#define GP31_REG ((volatile uint8_t *)0xFEC02134) +#define GP32_REG ((volatile uint8_t *)0xFEC02135) +#define GP33_REG ((volatile uint8_t *)0xFEC02136) +#define GP34_REG ((volatile uint8_t *)0xFEC02137) +#define GP35_REG ((volatile uint8_t *)0xFEC02138) +#define GP36_REG ((volatile uint8_t *)0xFEC02139) +#define GP37_REG ((volatile uint8_t *)0xFEC0213A) -#define GP1_REG ((volatile unsigned char *)0xFEC0214B) -#define GP2_REG ((volatile unsigned char *)0xFEC0214C) -#define GP3_REG ((volatile unsigned char *)0xFEC0214D) -#define GP4_REG ((volatile unsigned char *)0xFEC0214E) -#define GP5_REG ((volatile unsigned char *)0xFEC0214F) -#define GP6_REG ((volatile unsigned char *)0xFEC02150) +#define GP40_REG ((volatile uint8_t *)0xFEC0213B) +#define GP41_REG ((volatile uint8_t *)0xFEC0213C) +#define GP42_REG ((volatile uint8_t *)0xFEC0213D) +#define GP43_REG ((volatile uint8_t *)0xFEC0213E) -#define FAN1_REG ((volatile unsigned char *)0xFEC02156) -#define FAN2_REG ((volatile unsigned char *)0xFEC02157) -#define FAN_CTRL_REG ((volatile unsigned char *)0xFEC02158) -#define FAN1_TACH_REG ((volatile unsigned char *)0xFEC02159) -#define FAN2_TACH_REG ((volatile unsigned char *)0xFEC0215A) -#define FAN1_PRELOAD_REG ((volatile unsigned char *)0xFEC0215B) -#define FAN2_PRELOAD_REG ((volatile unsigned char *)0xFEC0215C) +#define GP50_REG ((volatile uint8_t *)0xFEC0213F) +#define GP51_REG ((volatile uint8_t *)0xFEC02140) +#define GP52_REG ((volatile uint8_t *)0xFEC02141) +#define GP53_REG ((volatile uint8_t *)0xFEC02142) +#define GP54_REG ((volatile uint8_t *)0xFEC02143) +#define GP55_REG ((volatile uint8_t *)0xFEC02144) +#define GP56_REG ((volatile uint8_t *)0xFEC02145) +#define GP57_REG ((volatile uint8_t *)0xFEC02146) -#define LED1_REG ((volatile unsigned char *)0xFEC0215D) -#define LED2_REG ((volatile unsigned char *)0xFEC0215E) -#define KEYBOARD_SCAN_CODE ((volatile unsigned char *)0xFEC0215F) +#define GP60_REG ((volatile uint8_t *)0xFEC02147) +#define GP61_REG ((volatile uint8_t *)0xFEC02148) + +#define GP1_REG ((volatile uint8_t *)0xFEC0214B) +#define GP2_REG ((volatile uint8_t *)0xFEC0214C) +#define GP3_REG ((volatile uint8_t *)0xFEC0214D) +#define GP4_REG ((volatile uint8_t *)0xFEC0214E) +#define GP5_REG ((volatile uint8_t *)0xFEC0214F) +#define GP6_REG ((volatile uint8_t *)0xFEC02150) + +#define FAN1_REG ((volatile uint8_t *)0xFEC02156) +#define FAN2_REG ((volatile uint8_t *)0xFEC02157) +#define FAN_CTRL_REG ((volatile uint8_t *)0xFEC02158) +#define FAN1_TACH_REG ((volatile uint8_t *)0xFEC02159) +#define FAN2_TACH_REG ((volatile uint8_t *)0xFEC0215A) +#define FAN1_PRELOAD_REG ((volatile uint8_t *)0xFEC0215B) +#define FAN2_PRELOAD_REG ((volatile uint8_t *)0xFEC0215C) + +#define LED1_REG ((volatile uint8_t *)0xFEC0215D) +#define LED2_REG ((volatile uint8_t *)0xFEC0215E) +#define KEYBOARD_SCAN_CODE ((volatile uint8_t *)0xFEC0215F) #endif