Corrections for interrupt race condition
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97cedc8659
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7641982319
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@ -492,19 +492,12 @@ SYSTEMCALL void int_clear(unsigned short n) {
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void int_handle_irq() {
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uint8_t mask_bits = 0;
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// vky_text_matrix[0] += 1;
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// if (*irq_ram_vector != 0) {
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// p_int_handler handler = (p_int_handler)(*irq_ram_vector);
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// handler();
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// return;
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// }
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// vky_text_matrix[1] += 1;
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// Process any pending interrupts in group 0
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mask_bits = *PENDING_GRP0;
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if (mask_bits) {
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// Clear the pending bits for group 0
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*PENDING_GRP0 = mask_bits;
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if ((mask_bits & 0x01) && int_handle_00) int_handle_00(); // Start of frame
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if ((mask_bits & 0x02) && int_handle_01) int_handle_01(); // Start of line
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if ((mask_bits & 0x04) && int_handle_02) int_handle_02(); // PS/2 Keyboard
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@ -513,42 +506,31 @@ void int_handle_irq() {
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if ((mask_bits & 0x20) && int_handle_05) int_handle_05(); // Timer 1
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if ((mask_bits & 0x40) && int_handle_06) int_handle_06(); // Reserved
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if ((mask_bits & 0x80) && int_handle_07) int_handle_07(); // Cartridge
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// Clear the pending bits for group 0
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*PENDING_GRP0 = mask_bits;
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}
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// Process any pending interrupts in group 1
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mask_bits = *PENDING_GRP1;
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if (mask_bits) {
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volatile __attribute__((far)) char * text = (char *)0xafa000;
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*text = *text + 1;
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// Clear the pending bits for group 1
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*PENDING_GRP1 = mask_bits;
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if ((mask_bits & 0x01) && int_handle_10) {
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volatile __attribute__((far)) char * text = (char *)0xafa001;
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*text = *text + 1;
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int_handle_10(); // PS/2 Keyboard
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}
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if ((mask_bits & 0x00) && int_handle_10) int_handle_10(); // UART
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if ((mask_bits & 0x01) && int_handle_10) int_handle_10(); // UART
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if ((mask_bits & 0x10) && int_handle_14) int_handle_14(); // RTC
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if ((mask_bits & 0x20) && int_handle_15) int_handle_15(); // VIA
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if ((mask_bits & 0x40) && int_handle_16) int_handle_16(); // F256K Matrix Keyboard
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if ((mask_bits & 0x80) && int_handle_17) int_handle_17(); // SD card inserted
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// Clear the pending bits for group 1
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*PENDING_GRP1 = mask_bits;
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}
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// Process any pending interrupts in group 2
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mask_bits = *PENDING_GRP2;
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if (mask_bits) {
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if ((mask_bits & 0x01) && int_handle_20) int_handle_20(); // IED Data IN
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if ((mask_bits & 0x02) && int_handle_21) int_handle_21(); // IED Clock IN
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if ((mask_bits & 0x02) && int_handle_22) int_handle_22(); // IED ATN IN
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if ((mask_bits & 0x02) && int_handle_22) int_handle_23(); // IED SREQ IN
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// Clear the pending bits for group 2
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*PENDING_GRP2 = mask_bits;
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if ((mask_bits & 0x01) && int_handle_20) int_handle_20(); // IED Data IN
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if ((mask_bits & 0x02) && int_handle_21) int_handle_21(); // IED Clock IN
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if ((mask_bits & 0x04) && int_handle_22) int_handle_22(); // IED ATN IN
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if ((mask_bits & 0x08) && int_handle_22) int_handle_23(); // IED SREQ IN
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}
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}
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@ -7,6 +7,6 @@
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#define VER_MAJOR 1
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#define VER_MINOR 1
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#define VER_BUILD 20
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#define VER_BUILD 23
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#endif
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