Peter Weingartner
5da0ebc7a7
SYSINFO Changes
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Changes to the system information record to better match the FPGA's registers and to more dynamically determine machine ID, CPU, clock speed, etc. Added clock speed to the record, and removed some fields that may not be useful.
2022-04-09 20:00:37 -04:00
Peter Weingartner
3afee6d912
Update test help printing and BUILD
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Added a work around for the TEST help printing code. Added a script to auto-generate a build number.
2021-12-06 20:25:59 -05:00
Peter Weingartner
fc9605a724
sys_get_info
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Updated sys_get_info and connections to FPGA registers.
2021-11-12 16:42:24 -05:00
Peter Weingartner
fbfd65a933
TESTMEM
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Added a memory test command.
2021-10-31 20:29:47 -04:00
Peter Weingartner
1db976edb5
Added PANIC and version info
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Added a panic screen that should come up for various exceptions. Made a few other minor changes.
2021-10-19 20:35:41 -04:00
Peter Weingartner
bfda2d4038
Started RTC Support and Test CMDs
2021-10-05 15:51:53 -04:00
Peter Weingartner
1a3e3d79f5
Some refactoring and FSYS
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Some refactoring of debug/tracing code and additions to FSYS and system information routines.
2021-09-22 16:08:09 -04:00
Peter Weingartner
3c073aa35c
Initial text driver work for VICKY III
2021-09-11 22:05:36 -04:00
