FoenixMCP

gered/FoenixMCP

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Author	SHA1	Message	Date
Peter Weingartner	fc9605a724	sys_get_info Updated sys_get_info and connections to FPGA registers.	2021-11-12 16:42:24 -05:00
Peter Weingartner	002b7decf0	Interrupts and Jiffies Fixed some interrupt issues on the U and converted the TICKS millisecond timer to be a jiffy (1/60s) timer based on the SOF interrupt. There are still some issue managing the RTC periodic interrupt.	2021-11-08 15:39:32 -05:00

Author

SHA1

Message

Date

Peter Weingartner

fc9605a724

sys_get_info

Updated sys_get_info and connections to FPGA registers.

2021-11-12 16:42:24 -05:00

Peter Weingartner

002b7decf0

Interrupts and Jiffies

Fixed some interrupt issues on the U and converted the TICKS millisecond timer to be a jiffy (1/60s) timer based on the SOF interrupt. There are still some issue managing the RTC periodic interrupt.

2021-11-08 15:39:32 -05:00

2 commits