Changes from Stefany for new A2560's

That is, the new machines with either a 68040 or 68060.

foenixmgr.ini

@@ -1,5 +1,5 @@
 [DEFAULT]
-port=COM3
+port=COM18
 labels=sample.lbl
 flash_address=380000
 chunk_size=1024

src/CompileFlash.bat

@@ -1,2 +1,3 @@
-set VBCC=d:/FoenixMCP/vbcc
+d:\make-3.81-bin\bin\make clean all
+set VBCC=d:/FoenixMCP-main-vince/vbcc
 d:\make-3.81-bin\bin\make all UNIT=a2560k MEMORY=flash

src/CompileFlashGenX.bat

@@ -1,3 +1,3 @@
 d:\make-3.81-bin\bin\make clean all
-set VBCC=d:/FoenixMCP/vbcc
+set VBCC=d:/FoenixMCP-main-vince/vbcc
 d:\make-3.81-bin\bin\make all UNIT=genx MEMORY=flash

src/CompileFlash_A2560X.bat

@@ -1,3 +1,3 @@
 d:\make-3.81-bin\bin\make clean all
-set VBCC=d:/FoenixMCP/vbcc
+set VBCC=d:/FoenixMCP-main-vince/vbcc
 d:\make-3.81-bin\bin\make all UNIT=a2560x MEMORY=flash

src/CompileRAMGenX.bat

@@ -1,3 +1,3 @@
 d:\make-3.81-bin\bin\make clean all
-set VBCC=d:/FoenixMCP/vbcc
+set VBCC=d:/FoenixMCP-main-vince/vbcc
 d:\make-3.81-bin\bin\make all UNIT=genx MEMORY=ram

src/CompileRAM_A2560K.bat

@@ -0,0 +1,2 @@
+set VBCC=d:/FoenixMCP-main-vince/vbcc
+d:\make-3.81-bin\bin\make all UNIT=a2560k MEMORY=ram

src/CompileRAM_A2560X.bat

@@ -1,3 +1,3 @@
 d:\make-3.81-bin\bin\make clean all
-set VBCC=d:/FoenixMCP/vbcc
+set VBCC=d:/FoenixMCP-main-vince/vbcc
 d:\make-3.81-bin\bin\make all UNIT=a2560x MEMORY=ram

src/Makefile

@@ -2,8 +2,8 @@
 # User may over-ride the UNIT and MEMORY parameters to specify target machine
 # and where the MCP will run (ram or flash)
 #
-UNIT := C256U_PLUS
+UNIT := a2560k
-MEMORY := ram
+MEMORY := flash
 
 # The script expects the following environment variables to be set:
 # VBCC: path to VBCC distribution 
@@ -11,7 +11,10 @@ MEMORY := ram
 # Define OS-dependent tools ---------------------------------------------------
 ifeq ("$(PAD_FLASH_SIZE)","")
 	# When compiling an image for flash, size to which the image must be padded
-	PAD_FLASH_SIZE = 524288
+	PAD_FLASH_SIZE = 524288 #by having a small Picture for the Splash screen, everything falls into 512K
+#the flash size in GenX/A2560X/A2560K is 4Meg not 512K	
+	#PAD_FLASH_SIZE = 655360	
+
 endif
 ifeq ($(OS),Windows_NT)
 	RM = del /F/Q
@@ -96,10 +99,11 @@ endif
 # VERBOSE 5   Log a truly verbose message... the sort you almost never want to bother with
 # Log message above DEFAULT_LOG_LEVEL level will not even be compiled, 
 # ie they will have NO chance of being output even if log_level is high enough.
-DEFAULT_LOG_LEVEL=1
+DEFAULT_LOG_LEVEL=2
 
 
 # Common defines and includes -------------------------------------------------
+#DEFINES = -DCPU=$(CPU_NUMBER) -DMODEL=$(MODEL_NUMBER) -DKBD_POLLED 
 DEFINES = -DCPU=$(CPU_NUMBER) -DMODEL=$(MODEL_NUMBER) # -DKBD_POLLED 
 ifeq ("$(CPU)","w65816")
 	CPU_NUMBER = 255
@@ -116,14 +120,14 @@ endif
 #define LOG_DEBUG   3   /* Log a debugging message */
 #define LOG_TRACE   4   /* Log tracing information (like entry into a subroutine) */
 #define LOG_VERBOSE 5   /* Log a truly verbose message... the sort you almost never want to bother with */
-DEFAULT_LOG_LEVEL=0
+DEFAULT_LOG_LEVEL=2
 
 #define LOG_CHANNEL_CHANNEL_A 0
 #define LOG_CHANNEL_CHANNEL_B 1
 #define LOG_CHANNEL_CHANNEL_A_LOW_LEVEL 2 // low-level routines (doesn't use MCP's console stuff)
 #define LOG_CHANNEL_COM1 10
 #define LOG_CHANNEL_COM2 11
-LOG_CHANNEL=11
+LOG_CHANNEL=10
 
 ifeq ("$(DEFAULT_LOG_LEVEL)","")
 else
@@ -195,7 +199,7 @@ else
 		CFLAGS_EXTRA=-D__NOINLINE__
 	else
 	endif	
-	CFLAGS =-c -S -cpu=$(VBCC_CPU) +$(CFG_FILE) $(CFLAGS_EXTRA)
+	CFLAGS =-c -S -k -cpu=$(VBCC_CPU) +$(CFG_FILE) $(CFLAGS_EXTRA) -O2
 	LDFLAGS = +$(CFG_FILE)
 endif
 
@@ -220,7 +224,7 @@ cpu_c_src := $(wildcard $(CPU)/*.c)
 cpu_obj := $(subst .c,.o,$(cpu_c_src)) $(subst .s,.o,$(cpu_s_src))
 
 # Device drivers (common to all Foenix)
-dev_c_src = block.c channel.c console.c fsys.c pata.c ps2.c rtc.c sdc.c txt_screen.c uart.c
+dev_c_src = block.c channel.c console.c fsys.c pata.c ps2.c rtc.c sdc_new.c txt_screen.c uart.c
 dev_s_src =
 ifeq ($(UNIT),a2560k)
 	dev_c_src := $(dev_c_src) fdc.c kbd_mo.c lpt.c midi.c txt_a2560k_a.c txt_a2560k_b.c superio.c

src/boot.c

@@ -213,9 +213,6 @@ short boot_screen(void) {
     // We'll display boot information on the common screen
     screen = 0;
 
-    /* Turn off the screen */
-    txt_set_mode(screen, TXT_MODE_SLEEP);
-
     for (i = 0; i < 256; i++) {
         LUT_0[4*i+0] = splashscreen_lut[4*i+0]; 
         LUT_0[4*i+1] = splashscreen_lut[4*i+1];
@@ -223,6 +220,8 @@ short boot_screen(void) {
         LUT_0[4*i+3] = splashscreen_lut[4*i+3];
     }
 
+    /* Turn off the screen */
+    txt_set_mode(screen, VID_SLEEP_GENX);
 #if 1
     /* Copy the bitmap to video RAM, it has simple RLE compression */
     for (pixels = splashscreen_pix; *pixels != 0;) {
@@ -232,6 +231,7 @@ short boot_screen(void) {
             *vram++ = color;
         }
     }
+    txt_set_mode(screen, TXT_MODE_TEXT | TXT_MODE_BITMAP | TXT_MODE_SPRITE);    
 #else
  #if 0
     // For debug, try something more basic
@@ -247,6 +247,7 @@ short boot_screen(void) {
     *BM0_Addy_Pointer_Reg = 0; /* Start of VRAM */
     *BM0_Control_Reg = 1; /* Enable bitmap layer, use LUT 0 */
 
+
     /* Set a background color for the bitmap mode */
 #if HAS_DUAL_SCREEN
     *BackGroundControlReg_B = 0x00202020;
@@ -267,7 +268,7 @@ short boot_screen(void) {
     region.size.height = 0;
     txt_set_region(screen, &region);
     txt_setsizes(screen);
-    txt_set_mode(screen, TXT_MODE_TEXT | TXT_MODE_BITMAP);
+    txt_set_mode(screen, TXT_MODE_TEXT | TXT_MODE_BITMAP | TXT_MODE_SPRITE);
 
     /* Disable the cursor, set the color, clear the text screen, and display the text message */
     txt_set_cursor(screen, 0, 0, 0);    // Disable the cursor
@@ -356,6 +357,7 @@ short boot_screen(void) {
     txt_init_screen(screen); /* This is the one used for the boot message */
     /* No need to txt_set_resolution(screen, 0, 0) because during screen_init, the defaults are applied */
 #if MODEL == MODEL_FOENIX_A2560K || MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_GENX
+    txt_set_resolution(0, 0, 0);    // Set the resolution based on the DIP switch
     txt_set_resolution(1, 0, 0);    // Set the resolution based on the DIP switch
 #endif
     print(screen, buffer);

src/c256.ini

@@ -1,4 +1,4 @@
 [DEFAULT]
-port=COM5
+port=COM48
 labels=sample.lbl
 flash_address=010000

src/dev/sdc_new.c

@@ -0,0 +1,922 @@
+/*------------------------------------------------------------------------/
+/  Foolproof MMCv3/SDv1/SDv2 (in SPI mode) control module
+/-------------------------------------------------------------------------/
+/
+/  Copyright (C) 2019, ChaN, all right reserved.
+/
+/ * This software is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-------------------------------------------------------------------------/
+  Features and Limitations:
+
+  * Easy to Port Bit-banging SPI
+    It uses only four GPIO pins. No complex peripheral needs to be used.
+
+  * Platform Independent
+    You need to modify only a few macros to control the GPIO port.
+
+  * Low Speed
+    The data transfer rate will be several times slower than hardware SPI.
+
+  * No Media Change Detection
+    Application program needs to perform a f_mount() after media change.
+
+/-------------------------------------------------------------------------*/
+
+#include <stdio.h>
+//#include "ff.h"		/* Obtains integer types for FatFs */
+#include "log_level.h"
+#ifndef DEFAULT_LOG_LEVEL
+    #define DEFAULT_LOG_LEVEL LOG_INFO
+#endif
+
+#include "log.h"
+#include "constants.h"
+#include "errors.h"
+#include "gabe_reg.h"
+#include "indicators.h"
+#include "interrupt.h"
+#include "dev/block.h"
+#include "sdc_reg.h"
+#include "dev/rtc.h"
+#include "dev/sdc_new.h"	/* Common include file for FatFs and disk I/O layer */
+//#include "dev/sdc.h"
+// Constant (4 the GenX/A2560K/A2560X)
+#define SDC_TIMEOUT_JF 20           /* Timeout in jiffies (1/60 second) */
+
+/*-------------------------------------------------------------------------*/
+/* Platform dependent macros and functions needed to be modified           */
+/*-------------------------------------------------------------------------*/
+// A2560K  $FEC00518
+#if MODEL == MODEL_FOENIX_A2560K
+#define SD0_STAT         ((volatile unsigned int *)0xFEC00518)
+#define SD0_STAT_CD      0x01000000      /* Is an SD card present? --- 0:Yes, 1:No */
+#define SD0_STAT_WP      0x02000000  /* Is the SD card write protected? --- 0:Yes, 1:No */
+// Gen X
+#elif MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_GENX
+#define SD0_STAT         ((volatile unsigned short *)0xFEC0051A)
+#define SD0_STAT_CD      0x0100      /* Is an SD card present? --- 0:Yes, 1:No */
+#define SD0_STAT_WP      0x0200      /* Is the SD card write protected? --- 0:Yes, 1:No */
+#endif 
+/* SPI Controler 0 Registers - External Access (Front of Unit)*/
+#define SD0_CTRL    ((volatile unsigned char *)0xFEC00300)
+#define SD0_DATA	((volatile unsigned char *)0xFEC00301)
+// Flags
+#define SDx_CS				0x01		// 1 = Enable 
+#define SDx_SLOW 			0x02		// 1 = Slow 400Khz, 0 = 25Mhz
+#define SDx_BUSY			0x80		// 1 = Busy
+// 
+#define DEV_SD0		0	/* Frontal SDCard - Removable Media 0 - SDCARD */
+//
+/* MMC card type flags (MMC_GET_TYPE) */
+#define CT_MMC3		0x01		/* MMC ver 3 */
+#define CT_MMC4		0x02		/* MMC ver 4+ */
+#define CT_MMC		0x03		/* MMC */
+#define CT_SDC1		0x04		/* SD ver 1 */
+#define CT_SDC2		0x08		/* SD ver 2+ */
+#define CT_SDC		0x0C		/* SD */
+#define CT_BLOCK	0x10		/* Block addressing */
+
+/* Delay n microseconds (avr-gcc -Os) */
+static void dly_us (unsigned int n)	{
+	do {
+    // Add Timer Routine for 1us (33Mhz (each fetch from flash takes 4 clock cycles))
+	// So for 1 us, it is about 8 to 10 instructions. Now the cache is off, probably won't work if cache is on.
+    __asm("   nop\n"
+          "   nop\n"
+          "   nop\n"
+          "   nop\n"
+          "   nop\n"
+          "   nop\n"
+		  "   nop\n"
+		  "   nop\n"
+		  "   nop\n"
+		  "   nop\n");
+	} while (--n);
+}
+/*--------------------------------------------------------------------------
+
+   Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+/* MMC/SD command (SPI mode) */
+#define CMD0	(0)			/* GO_IDLE_STATE */
+#define CMD1	(1)			/* SEND_OP_COND */
+#define	ACMD41	(0x80+41)	/* SEND_OP_COND (SDC) */
+#define CMD8	(8)			/* SEND_IF_COND */
+#define CMD9	(9)			/* SEND_CSD */
+#define CMD10	(10)		/* SEND_CID */
+#define CMD12	(12)		/* STOP_TRANSMISSION */
+#define CMD13	(13)		/* SEND_STATUS */
+#define ACMD13	(0x80+13)	/* SD_STATUS (SDC) */
+#define CMD16	(16)		/* SET_BLOCKLEN */
+#define CMD17	(17)		/* READ_SINGLE_BLOCK */
+#define CMD18	(18)		/* READ_MULTIPLE_BLOCK */
+#define CMD23	(23)		/* SET_BLOCK_COUNT */
+#define	ACMD23	(0x80+23)	/* SET_WR_BLK_ERASE_COUNT (SDC) */
+#define CMD24	(24)		/* WRITE_BLOCK */
+#define CMD25	(25)		/* WRITE_MULTIPLE_BLOCK */
+#define CMD32	(32)		/* ERASE_ER_BLK_START */
+#define CMD33	(33)		/* ERASE_ER_BLK_END */
+#define CMD38	(38)		/* ERASE */
+#define CMD55	(55)		/* APP_CMD */
+#define CMD58	(58)		/* READ_OCR */
+
+
+static unsigned char SD0_Stat = STA_NOINIT;	/* Disk status */
+static unsigned char SD0_CardType;			/* b0:MMC, b1:SDv1, b2:SDv2, b3:Block addressing */
+
+unsigned char g_sdc_status = SDC_STAT_NOINIT;
+unsigned char g_sdc_error = 0;
+
+
+
+////////////////////////////////////////////////////////////////////////////
+/// STEFANY's CODE STARTS HERE
+/*-----------------------------------------------------------------------*/
+/* Transmit Busy Flag Check - SPI Controler 0                          */
+/*-----------------------------------------------------------------------*/
+static void SD0_Wait_SDx_Busy( void ) {
+	unsigned char i;
+	i = (*SD0_CTRL & SDx_BUSY);
+	do {
+		i = (*SD0_CTRL & SDx_BUSY);
+	} while (i == SDx_BUSY);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Transmit bytes to the card - SPI Controler 0                          */
+/*-----------------------------------------------------------------------*/
+static void SD0_Tx ( const unsigned char* buff,	unsigned int bc ) {
+	unsigned char d;
+	do {
+		d = *buff++;	/* Get a byte to be sent */
+    *SD0_DATA = d; // Set the Data in the Transmit Register
+    SD0_Wait_SDx_Busy(); // Wait for the transmit to be over with 
+	} while (--bc);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Receive bytes from the card - SPI Controler 0                         */
+/*-----------------------------------------------------------------------*/
+static void SD0_Rx ( unsigned char *buff, unsigned int bc	) {
+	unsigned char r;
+	do {
+    	*SD0_DATA = 0xff; // Set the Data in the Transmit Register
+    	SD0_Wait_SDx_Busy(); // Wait for the transmit to be over with 
+			*buff++ = *SD0_DATA;			/* Store a received byte */
+	} while (--bc);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Wait for card ready Using - SPI Controler 0                           */
+/*-----------------------------------------------------------------------*/
+static int SD0_wait_ready (void) {
+	unsigned char d;
+	unsigned int tmr;
+	for (tmr = 5000; tmr; tmr--) {	/* Wait for ready in timeout of 500ms */
+		SD0_Rx(&d, 1);
+		if (d == 0xFF) break;
+		dly_us(100);              // 100us
+	}
+	return tmr ? 1 : 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Deselect the card and release SPI bus - SPI Controler 0               */
+/*-----------------------------------------------------------------------*/
+static void SD0_deselect ( void ) {
+	unsigned char d;
+  *SD0_CTRL = *SD0_CTRL & ~ SDx_CS; // SDx_CS = 0 ( Disabled ), SDx = 1 (Active)
+	SD0_Rx(&d, 1);	/* Dummy clock (force DO hi-z for multiple slave SPI) */
+}
+
+/*-----------------------------------------------------------------------*/
+/* Select the card and wait for ready - SPI Controler 0                  */
+/*-----------------------------------------------------------------------*/
+/* 1:OK, 0:Timeout */
+static int SD0_select (void) {
+	unsigned char d;
+
+  *SD0_CTRL = *SD0_CTRL | SDx_CS; // SDx_CS = 0 ( Disabled ), SDx = 1 (Active)
+	SD0_Rx(&d, 1);	/* Dummy clock (force DO enabled) */
+	
+  if (SD0_wait_ready()) 
+    return 1;	/* Wait for card ready */
+
+	SD0_deselect();
+	return 0;			/* Failed */
+}
+
+/*-----------------------------------------------------------------------*/
+/* Receive a data packet from the card  - SPI Controler 0                */
+/*-----------------------------------------------------------------------*/
+/* 1:OK, 0:Failed */
+static int SD0_Rx_datablock ( unsigned char *buff, unsigned int btr ) {
+	unsigned char d[2];
+	unsigned int tmr;
+
+	for (tmr = 1000; tmr; tmr--) {	/* Wait for data packet in timeout of 100ms */
+		SD0_Rx(d, 1);
+		if (d[0] != 0xFF) break;
+		dly_us(100);    // 100us
+	}
+
+	if (d[0] != 0xFE) 
+    return 0;		/* If not valid data token, return with error */
+
+	SD0_Rx(buff, btr);			/* Receive the data block into buffer */
+	SD0_Rx(d, 2);					/* Discard CRC */
+
+	return 1;						/* Return with success */
+}
+
+/*-----------------------------------------------------------------------*/
+/* Send a data packet to the card  - SPI Controler 0                     */
+/*-----------------------------------------------------------------------*/
+/* 1:OK, 0:Failed */
+static int SD0_Tx_datablock (	const unsigned char *buff,	unsigned char token ) {
+	unsigned char d[2];
+
+	if (!SD0_wait_ready()) 
+    return 0;
+
+	d[0] = token;
+	SD0_Tx(d, 1);				/* Xmit a token */
+
+	if (token != 0xFD) {		/* Is it data token? */
+		SD0_Tx(buff, 512);	/* Xmit the 512 byte data block to MMC */
+		SD0_Rx(d, 2);			/* Xmit dummy CRC (0xFF,0xFF) */
+		SD0_Rx(d, 1);			/* Receive data response */
+		if ((d[0] & 0x1F) != 0x05)	/* If not accepted, return with error */
+			return 0;
+	}
+
+	return 1;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Send a command packet to the card                                     */
+/*-----------------------------------------------------------------------*/
+/* Returns command response (bit7==1:Send failed)*/
+static unsigned char SD0_Tx_cmd ( unsigned char cmd, unsigned long arg ) {
+	unsigned char n, d, buf[6];
+	//printf("Processing Command: %d\r", cmd);
+	if (cmd & 0x80) {	/* ACMD<n> is the command sequense of CMD55-CMD<n> */
+		cmd &= 0x7F;
+		n = SD0_Tx_cmd(CMD55, 0);
+		if (n > 1)
+      return n;
+	}
+
+	/* Select the card and wait for ready except to stop multiple block read */
+	if (cmd != CMD12) {
+		//printf("Processing Command: %d\r", cmd);		
+		SD0_deselect();
+		if (!SD0_select()) 
+      return 0xFF;
+	}
+
+	/* Send a command packet */
+	buf[0] = 0x40 | cmd;			/* Start + Command index */
+	buf[1] = (unsigned char)(arg >> 24);		/* Argument[31..24] */
+	buf[2] = (unsigned char)(arg >> 16);		/* Argument[23..16] */
+	buf[3] = (unsigned char)(arg >> 8);		/* Argument[15..8] */
+	buf[4] = (unsigned char)arg;				/* Argument[7..0] */
+	n = 0x01;						/* Dummy CRC + Stop */
+
+	if (cmd == CMD0) 
+    n = 0x95;		/* (valid CRC for CMD0(0)) */
+	if (cmd == CMD8) 
+    n = 0x87;		/* (valid CRC for CMD8(0x1AA)) */
+	
+  buf[5] = n;
+	SD0_Tx(buf, 6);
+
+	/* Receive command response */
+	if (cmd == CMD12) 
+    SD0_Rx(&d, 1);	/* Skip a stuff byte when stop reading */
+	
+  n = 10;								/* Wait for a valid response in timeout of 10 attempts */
+	do
+		SD0_Rx(&d, 1);
+	while ((d & 0x80) && --n);
+
+	return d;			/* Return with the response value */
+}
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+---------------------------------------------------------------------------*/
+
+//#define SD0_STAT      (*(volatile __far uint8_t *)0xF016A0)
+//#define SD0_STAT_CD   0x40  // When 1 = No Card, 0 = Card is Present
+//#define SD0_STAT_WP   0x80  // When 1 = Writeable, 0 = Card is Protected
+/*-----------------------------------------------------------------------*/
+/* Get Disk Status                                                       */
+/*-----------------------------------------------------------------------*/
+/* Drive number (always 0) */
+/*
+unsigned char disk_status ( BYTE drv ) {
+
+  if ( drv == DEV_SD0) {
+  // CHeck for Card Present
+    if ( *SD0_STAT & SD0_STAT_CD )
+      g_sdc_status = g_sdc_status | STA_NODISK;
+    else 
+      g_sdc_status = g_sdc_status & ~STA_NODISK;
+
+    if ( *SD0_STAT & SD0_STAT_WP )
+      g_sdc_status = g_sdc_status | STA_PROTECT;
+    else 
+      g_sdc_status = g_sdc_status & ~STA_PROTECT;
+    return g_sdc_status;
+  }
+
+  return STA_NOINIT;
+}
+*/
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+unsigned char new_disk_initialize (
+	unsigned char drv		/* Physical drive nmuber (0) */
+)
+{
+	unsigned char n, ty, cmd, buf[4];
+	unsigned int tmr;
+	unsigned char s;
+
+	//printf("Init Drive %d\r", drv);	
+	dly_us(10000);			/* 10ms */
+    *SD0_CTRL = *SD0_CTRL | SDx_SLOW;   // Set the SPI in Slow Mode
+	  for (n = 10; n; n--) {
+	  	SD0_Rx(buf, 1);	/* Apply 80 dummy clocks and the card gets ready to receive command */
+	  }
+	  ty = 0;
+	  if (SD0_Tx_cmd(CMD0, 0) == 1) {			/* Enter Idle state */
+
+	  	if (SD0_Tx_cmd(CMD8, 0x1AA) == 1) {	/* SDv2? */
+	  		SD0_Rx(buf, 4);							/* Get trailing return value of R7 resp */
+	  		if (buf[2] == 0x01 && buf[3] == 0xAA) {		/* The card can work at vdd range of 2.7-3.6V */
+	  			for (tmr = 1000; tmr; tmr--) {			/* Wait for leaving idle state (ACMD41 with HCS bit) */
+	  				if (SD0_Tx_cmd(ACMD41, 1UL << 30) == 0) break;
+	  				dly_us(1000);
+	  			}
+	  			if (tmr && SD0_Tx_cmd(CMD58, 0) == 0) {	/* Check CCS bit in the OCR */
+	  				SD0_Rx(buf, 4);
+	  				ty = (buf[0] & 0x40) ? CT_SDC2 | CT_BLOCK : CT_SDC2;	/* SDv2+ */
+	  			}
+	  		}
+	  	} else {							/* SDv1 or MMCv3 */
+	  		if (SD0_Tx_cmd(ACMD41, 0) <= 1) 	{
+	  			ty = CT_SDC2; cmd = ACMD41;	/* SDv1 */
+	  		} else {
+	  			ty = CT_MMC3; cmd = CMD1;	/* MMCv3 */
+	  		}
+	  		for (tmr = 1000; tmr; tmr--) {			/* Wait for leaving idle state */
+	  			if (SD0_Tx_cmd(cmd, 0) == 0) 
+					break;
+	  			dly_us(1000);
+	  		}
+	  		if (!tmr || SD0_Tx_cmd(CMD16, 512) != 0)	/* Set R/W block length to 512 */
+	  			ty = 0;
+	  	}
+	  }
+      *SD0_CTRL = *SD0_CTRL & ~SDx_SLOW;   // Bring back the Fast Mode - 25Mhz
+
+	  SD0_CardType = ty;
+	  s = ty ? 0 : STA_NOINIT;
+	  g_sdc_status = s;
+	  SD0_deselect();
+	
+	//DEBUG1("sdc_init: sdtype=0x%x", (unsigned char)ty);
+    //log3(LOG_INFO, "cli_exec: '", argv[0], "'");
+    //log_num(LOG_INFO, "argc = ", argc);	
+		if (s) {
+	  	  logmsg(LOG_ERROR, "SDC_INIT <--- S > 0");
+		}
+		else {
+			logmsg(LOG_ERROR, "SDC_INIT <--- S == 0");
+			log_num(LOG_INFO, "SDC_INIT <--- SDCard Type:", (unsigned char)ty);
+		}
+
+	  return s;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s)                                                        */
+/*-----------------------------------------------------------------------*/
+
+unsigned char new_disk_read (unsigned char drv,	unsigned char *buff, unsigned long sector, unsigned short count ) {
+	unsigned char cmd;
+	unsigned long sect = (unsigned long)sector;
+
+	logmsg(LOG_INFO, "...Entering SDC_DISK_READ");
+
+//	if (disk_status(drv) & STA_NOINIT) 
+//    	return RES_NOTRDY;
+
+	if (!(SD0_CardType & CT_BLOCK))
+    	sect *= 512;	/* Convert LBA to byte address if needed */
+
+	log_num(LOG_INFO, "SDC_DISK_READ <--- Count = ", count);
+	cmd = count > 1 ? CMD18 : CMD17;			/*  READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */
+	log_num(LOG_INFO, "SDC_DISK_READ <--- Command:", (unsigned char)cmd);
+
+	if (SD0_Tx_cmd(cmd, sect) == 0) {
+		do {
+	  		if (!SD0_Rx_datablock(buff, 512)) 
+          		break;
+	  		buff += 512;
+	  	} while (--count);
+	  	
+		if (cmd == CMD18) 
+    	SD0_Tx_cmd(CMD12, 0);	/* STOP_TRANSMISSION */
+	}
+	SD0_deselect();
+	log_num(LOG_INFO, "SDC_DISK_READ <--- End Count = ", count);
+  return count ? RES_ERROR : RES_OK;      
+}
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s)                                                       */
+/*-----------------------------------------------------------------------*/
+//DRESULT disk_write (
+//	BYTE drv,			/* Physical drive nmuber (0) */
+//	const BYTE *buff,	/* Pointer to the data to be written */
+//	LBA_t sector,		/* Start sector number (LBA) */
+//	UINT count			/* Sector count (1..128) */
+//)
+unsigned char new_disk_write ( unsigned char drv, const unsigned char *buff, unsigned long sector, unsigned int count ) {
+	unsigned long sect = (unsigned long)sector;
+
+	//if (disk_status(drv) & STA_NOINIT) 
+	//return RES_NOTRDY;	
+
+	if (!(SD0_CardType & CT_BLOCK)) sect *= 512;	/* Convert LBA to byte address if needed */	
+	if (count == 1) {	/* Single block write */
+		if ((SD0_Tx_cmd(CMD24, sect) == 0) && SD0_Tx_datablock(buff, 0xFE))
+			count = 0;
+	}
+	else {				/* Multiple block write */
+		if (SD0_CardType & CT_SDC) 
+	  SD0_Tx_cmd(ACMD23, count);	
+		if (SD0_Tx_cmd(CMD25, sect) == 0) {	/* WRITE_MULTIPLE_BLOCK */
+			do {
+				if (!SD0_Tx_datablock(buff, 0xFC)) 
+	      break;
+				buff += 512;
+			} while (--count);	
+			if (!SD0_Tx_datablock(0, 0xFD))	/* STOP_TRAN token */
+				count = 1;
+		}
+	}
+	SD0_deselect();	
+  
+  return count ? RES_ERROR : RES_OK;
+}
+
+
+// Will implement later
+/*
+DWORD get_fattime (void)
+{
+    time_t t;
+    struct tm *stm;
+
+
+    t = time(0);
+    stm = localtime(&t);
+
+    return (DWORD)(stm->tm_year - 80) << 25 |
+           (DWORD)(stm->tm_mon + 1) << 21 |
+           (DWORD)stm->tm_mday << 16 |
+           (DWORD)stm->tm_hour << 11 |
+           (DWORD)stm->tm_min << 5 |
+           (DWORD)stm->tm_sec >> 1;
+}
+*/
+
+/*
+ * Handle insertion of an SD card
+ */
+void sdc_handler() {
+    /* Very simple... just flag it as uninitialized */
+    g_sdc_status = SDC_STAT_NOINIT;
+}
+//
+// Attempt to reset the SD controller
+// Stefany Note, March 18th, 2024:
+// Now that it is completely Controled in Software through SPI there is no core to reset
+void sdc_reset() {
+    short delay;
+    TRACE("sdc_reset");
+}
+//
+// Return true if there is an SD card in the slot
+//
+// When no Card Inserted, the bit ought to be 1
+// When a card is present the bit ought to be 0
+short sdc_detected() {
+    TRACE("sdc_detected()");
+	if (( *GABE_SDC_REG & GABE_SDC_PRESENT ) == 0 )
+		return (1);
+	else 
+		return (0);
+
+    //return (*GABE_SDC_REG & GABE_SDC_PRESENT) != GABE_SDC_PRESENT;
+}
+//
+// Return true if there is an SD card is protected
+//
+short sdc_protected() {
+    TRACE("sdc_protected()");
+    return (*GABE_SDC_REG & GABE_SDC_WPROT) == GABE_SDC_WPROT;
+}
+//
+// Turn the SDC LED on or off
+//
+// Inputs:
+//  is_on = if 0, turn the LED off, otherwise turn the LED on
+//
+void sdc_set_led(short is_on) {
+	ind_set(IND_SDC, is_on);
+}
+
+short sdc_init_n() {
+    TRACE("sdc_init");
+
+    // Check for presence of the card
+    if (!sdc_detected()) {
+        // SDC_DETECTED is active 0... 1 means there is no card
+        g_sdc_status = SDC_STAT_NOINIT;
+        return DEV_NOMEDIA;
+    }
+	new_disk_initialize( 0x00 ); // One SDCard in the system, so Device is 0
+							// The disk init directly sets the g_sdc_error
+
+    if ( g_sdc_error ) { // if g_sdc_error == 1 - STA_NOINIT
+        logmsg(LOG_ERROR, "sdc_init: DEV_CANNOT_INIT");
+        return DEV_CANNOT_INIT;
+    } 
+	else {	// if g_sdc_error == 0 == Success
+	    logmsg(LOG_INFO, "sdc_init: SUCCESS");
+    	return 0;		
+    }
+}
+
+
+//
+// Read a block from the SDC
+//
+// Inputs:
+//  lba = the logical block address of the block to read
+//  buffer = the buffer into which to copy the block data
+//  size = the size of the buffer.
+//
+// Returns:
+//  number of bytes read, any negative number is an error code
+//
+short sdc_read_n(long lba, unsigned char * buffer, short size) {
+	unsigned char status;
+	unsigned char cmd;
+	unsigned long sect = (unsigned long)lba;
+	unsigned short Count = size >> 9;	// Count is the number of packet of 512bytes
+	
+
+    TRACE3("sdc_read(%ld,%p,%d)", sect, buffer, (int)size);
+
+    // Check for presence of the card
+    if (!sdc_detected()) {
+        // SDC_DETECTED is active 0... 1 means there is no card
+        g_sdc_status = SDC_STAT_NOINIT;
+        TRACE("sdc_read: DEV_NOMEDIA");
+        return DEV_NOMEDIA;
+    }
+
+	logmsg(LOG_ERROR, "SDC_READ <--- About to Go Read A sector");
+    /* Turn on the SDC LED */
+    ind_set(IND_SDC, IND_ON);
+
+
+//unsigned char new_disk_read (unsigned char drv,	unsigned char *buff, unsigned long sector, unsigned int count ) 
+	//status = new_disk_read ( 0x00,	buffer, lba, size);
+	logmsg(LOG_INFO, "...Entering SDC_DISK_READ");
+
+//	if (disk_status(drv) & STA_NOINIT) 
+//    	return RES_NOTRDY;
+
+	if (!(SD0_CardType & CT_BLOCK))
+    	sect *= 512;	/* Convert LBA to byte address if needed */
+
+	log_num(LOG_INFO, "SDC_READ <--- Size Before = ", size);
+	log_num(LOG_INFO, "SDC_READ <--- Sector Before = ", sect);
+
+	//cmd = size > 1 ? CMD18 : CMD17;			/*  READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */
+	cmd = Count > 1 ? CMD18 : CMD17;			/*  READ_MULTIPLE_BLOCK : READ_SINGLE_BLOCK */
+
+	log_num(LOG_INFO, "SDC_DISK_READ <--- Command:", (unsigned char)cmd);
+
+	if (SD0_Tx_cmd(cmd, sect) == 0) {
+		logmsg(LOG_INFO, "SDC_READ <--- Pass the SD0_Tx_cmd");
+		do {
+	  		if (!SD0_Rx_datablock(buffer, 512)) 
+          		break;
+	  		buffer += 512;
+	  	} while (--Count);
+	  	
+		if (cmd == CMD18) 
+    	SD0_Tx_cmd(CMD12, 0);	/* STOP_TRANSMISSION */
+	}
+	SD0_deselect();
+	log_num(LOG_INFO, "SDC_DISK_READ <--- End Count = ", size);
+  	status = Count ? RES_ERROR : RES_OK;    
+
+	ind_set(IND_SDC, IND_OFF);
+// By this point, the indeed has been executed, so we can turn off LED
+// possible values for Status
+/* 	RES_OK = 0,		0: Successful */
+/* 	RES_ERROR,		1: R/W Error */
+/* 	RES_WRPRT,		2: Write Protected */
+/* 	RES_NOTRDY		3: Not Ready */
+/* 	RES_PARERR		4: Invalid Parameter */
+	log_num(LOG_INFO, "SDC_READ <--- Status = ", status);
+	switch ( status ) {
+		case RES_OK:  
+        	// Success: return the byte count
+			// With the old controller the Count was sent back because it was starting from 0
+			// in the new code the Count is actually decremented in the read routine, so I will just report the original Size
+            TRACE1("sdc_read: returning %d", size);
+            return size;		
+		break;
+
+		case RES_ERROR:
+            TRACE("sdc_read: DEV_CANNOT_READ");
+            return DEV_CANNOT_READ;
+		break;
+
+		case RES_NOTRDY:
+        	TRACE("sdc_read: DEV_NOMEDIA");		
+			return DEV_NOMEDIA; // No specific error for not readyu
+		break;
+
+		// Honestly the code ought to never reach that point
+		default: 
+			return ERR_GENERAL;
+		break;
+	}
+}
+//
+// Write a block to the SDC
+//
+// Inputs:
+//  lba = the TRACEical block address of the block to write
+//  buffer = the buffer containing the data to write
+//  size = the size of the buffer.
+//
+// Returns:
+//  number of bytes written, any negative number is an error code
+//
+short sdc_write_n(long lba, const unsigned char * buffer, short size) {
+	unsigned char status;
+	unsigned long sect = (unsigned long)lba;
+	unsigned short count = size >> 9;	// Count is the number of packet of 512bytes
+
+    TRACE("sdc_write");
+
+    // Check for presence of the card
+
+    if (!sdc_detected()) {
+        // SDC_DETECTED is active 0... 1 means there is no card
+        g_sdc_status = SDC_STAT_NOINIT;
+        return DEV_NOMEDIA;
+    }
+	logmsg(LOG_ERROR, "SDC_WRITE <--- About to Go Write A sector");
+    /* Turn on the SDC LED */
+    ind_set(IND_SDC, IND_ON);
+
+//	status = new_disk_write ( 0x00, buffer, lba, size );
+
+	//if (disk_status(drv) & STA_NOINIT) 
+	//return RES_NOTRDY;	
+
+	if (!(SD0_CardType & CT_BLOCK)) 
+		sect *= 512;	/* Convert LBA to byte address if needed */	
+	
+	if (count == 1) {	/* Single block write */
+		if ((SD0_Tx_cmd(CMD24, sect) == 0) && SD0_Tx_datablock(buffer, 0xFE))
+			count = 0;
+	}
+	else {				/* Multiple block write */
+		if (SD0_CardType & CT_SDC) 
+	  SD0_Tx_cmd(ACMD23, count);	
+		if (SD0_Tx_cmd(CMD25, sect) == 0) {	/* WRITE_MULTIPLE_BLOCK */
+			do {
+				if (!SD0_Tx_datablock(buffer, 0xFC)) 
+	      break;
+				buffer += 512;
+			} while (--count);	
+			if (!SD0_Tx_datablock(0, 0xFD))	/* STOP_TRAN token */
+				count = 1;
+		}
+	}
+	SD0_deselect();	
+  
+  status = count ? RES_ERROR : RES_OK;
+
+
+	ind_set(IND_SDC, IND_OFF);
+
+// By this point, the indeed has been executed, so we can turn off LED
+// possible values for Status
+/* 	RES_OK = 0,		0: Successful */
+/* 	RES_ERROR,		1: R/W Error */
+/* 	RES_WRPRT,		2: Write Protected */
+/* 	RES_NOTRDY		3: Not Ready */
+/* 	RES_PARERR		4: Invalid Parameter */
+
+	switch ( status ) {
+		case RES_OK:  
+        	// Success: return the byte count
+			// With the old controller the Count was sent back because it was starting from 0
+			// in the new code the Count is actually decremented in the read routine, so I will just report the original Size
+            TRACE1("sdc_write: returning %d", size);
+            return size;		
+		break;
+
+		case RES_ERROR:
+            TRACE("sdc_write: DEV_CANNOT_WRITE");
+            return DEV_CANNOT_WRITE;
+		break;
+
+		case RES_NOTRDY:
+        	TRACE("sdc_write: DEV_NOMEDIA");		
+			return DEV_NOMEDIA; // No specific error for not readyu
+		break;
+
+		// Honestly the code ought to never reach that point
+		default: 
+			return ERR_GENERAL;
+		break;
+	}
+}
+//
+// Return the status of the SDC
+//
+// Returns:
+//  the status of the device
+//
+short sdc_status_n() {
+    short status = g_sdc_status;
+	logmsg(LOG_ERROR, "SDC_STATUS");
+    TRACE1("sdc_status, status=0x%x",(int)status);
+
+    if (sdc_detected()) {
+        // Add the PRESENT flag, if the card is inserted
+        status |= SDC_STAT_PRESENT;
+    }
+
+    if (sdc_protected()) {
+        // Add the PROTECTED flag, if the card is write-protected
+        status |= SDC_STAT_PROTECTED;
+    }
+
+    TRACE1("sdc_status: %x", (short)status);
+    return status;
+}
+//
+// Return any error code of the SDC
+//
+// Returns:
+//  the error code of the device
+//
+short sdc_error_n() {
+    return g_sdc_error;
+}
+
+//
+// Ensure that any pending writes to teh device have been completed
+//
+// Returns:
+//  0 on success, any negative number is an error code
+//
+short sdc_flush_n() {
+    return 0;           // We don't buffer writes... always return success
+}
+
+//
+// Return the count of sectors in this SD card
+//
+short sdc_sector_count() {
+    // TODO: implement this!
+    return 1000;
+}
+
+#define SDC_GET_SECTOR_COUNT 1
+#define SDC_GET_SECTOR_SIZE 2
+#define SDC_GET_BLOCK_SIZE 3
+
+
+//
+// Issue a control command to the device
+//
+// Inputs:
+//  command = the number of the command to send
+//  buffer = pointer to bytes of additional data for the command
+//  size = the size of the buffer
+//
+// Returns:
+//  0 on success, any negative number is an error code
+//
+
+
+short sdc_ioctrl_n(short command, unsigned char * buffer, short size) {
+	unsigned char res;
+	unsigned char n, csd[16];
+	unsigned long cs;
+    unsigned short *p_word;
+
+//	if (disk_status(0) & STA_NOINIT) 
+//		return RES_NOTRDY;	/* Check if card is in the socket */	
+	logmsg(LOG_ERROR, "SDC_IOCONTROL <--- About to Pull Information");
+	res = RES_ERROR;
+	switch (command) {
+
+		// 0
+		case CTRL_SYNC :		/* Make sure that no pending write process */
+			if (SD0_select()) 
+			res = RES_OK;
+			break;	
+
+		// 1
+		case SDC_GET_SECTOR_COUNT :	/* Get number of sectors on the disk (DWORD) */
+			if ((SD0_Tx_cmd(CMD9, 0) == 0) && SD0_Rx_datablock(csd, 16)) {
+				if ((csd[0] >> 6) == 1) {	/* SDC ver 2.00 */
+					cs = csd[9] + ((unsigned short)csd[8] << 8) + ((unsigned long)(csd[7] & 63) << 16) + 1;
+					*(unsigned long*)buffer = cs << 10;
+				} 
+	    else {					/* SDC ver 1.XX or MMC */
+					n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
+					cs = (csd[8] >> 6) + ((unsigned short)csd[7] << 2) + ((unsigned short)(csd[6] & 3) << 10) + 1;
+					*(unsigned long*)buffer = cs << (n - 9);
+				}
+				res = RES_OK;
+			}
+		break;
+
+		case SDC_GET_SECTOR_SIZE:
+            // Return the size of a sector... always 512
+            p_word = (unsigned short *)buffer;
+            *p_word = SDC_SECTOR_SIZE;
+		break; 
+
+		// 	Block Size		
+		case GET_BLOCK_SIZE :	/* Get erase block size in unit of sector (DWORD) */
+			*(unsigned long*)buffer = 128;
+			res = RES_OK;
+			break;	
+		default:
+			res = RES_PARERR;
+	}
+	SD0_deselect();
+
+	return res;
+}
+
+//
+// Install the SDC driver
+//
+short sdc_install_n() {
+    t_dev_block dev;                    // bdev_register copies the data, so we'll allocate this on the stack
+
+    TRACE("sdc_install");
+
+    /* Install an interrupt handler to catch insertion of a card */
+    int_register(INT_SDC_INS, sdc_handler);
+    int_enable(INT_SDC_INS);
+
+    //sdc_reset(); - No Need for any reset here... Everything is now SPI and software control, no hardwire controller
+
+    dev.number = BDEV_SDC;
+    dev.name = "SDC";
+    dev.init = sdc_init_n;
+    dev.read = sdc_read_n;
+    dev.write = sdc_write_n;
+    dev.flush = sdc_flush_n;
+    dev.status = sdc_status_n;
+    dev.ioctrl = sdc_ioctrl_n;
+
+    return bdev_register(&dev);
+}

src/dev/sdc_new.h

@@ -0,0 +1,164 @@
+/*-----------------------------------------------------------------------/
+/  Low level disk interface modlue include file   (C)ChaN, 2019          /
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO_DEFINED
+#define _DISKIO_DEFINED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "types.h"
+
+/* Status of Disk Functions */
+//typedef unsigned char	DSTATUS;
+
+/* Results of Disk Functions */
+
+typedef enum {
+	RES_OK = 0,		/* 0: Successful */
+	RES_ERROR,		/* 1: R/W Error */
+	RES_WRPRT,		/* 2: Write Protected */
+	RES_NOTRDY,		/* 3: Not Ready */
+	RES_PARERR		/* 4: Invalid Parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+
+//unsigned char disk_initialize (unsigned char pdrv);
+//unsigned char disk_status (unsigned char pdrv);
+//unsigned char disk_read (unsigned char pdrv, unsigned char *buff, LBA_t sector, unsigned int count);
+//unsigned char disk_write (unsigned char pdrv, const unsigned char* buff, LBA_t sector, unsigned int count);
+//unsigned char disk_ioctl (unsigned char pdrv, unsigned char cmd, void* buff);
+
+
+
+//
+// Install the SDC driver
+//
+extern short sdc_install_n();
+
+//
+// Initialize the SDC
+//
+// Returns:
+//  0 on success, any negative number is an error code
+//
+extern short sdc_init_n();
+
+//
+// Read a block from the SDC
+//
+// Inputs:
+//  lba = the logical block address of the block to read
+//  buffer = the buffer into which to copy the block data
+//  size = the size of the buffer.
+//
+// Returns:
+//  number of bytes read, any negative number is an error code
+//
+extern short sdc_read_n(long lba, unsigned char * buffer, short size);
+
+//
+// Write a block to the SDC
+//
+// Inputs:
+//  lba = the logical block address of the block to write
+//  buffer = the buffer containing the data to write
+//  size = the size of the buffer.
+//
+// Returns:
+//  number of bytes written, any negative number is an error code
+//
+extern short sdc_write_n(long lba, const unsigned char * buffer, short size);
+
+//
+// Return the status of the SDC
+//
+// Returns:
+//  the status of the device
+//
+extern short sdc_status_n();
+
+//
+// Return any error code of the SDC
+//
+// Returns:
+//  the error code of the device
+//
+extern short sdc_error_n();
+
+//
+// Ensure that any pending writes to teh device have been completed
+//
+// Returns:
+//  0 on success, any negative number is an error code
+//
+extern short sdc_flush_n();
+
+//
+// Issue a control command to the device
+//
+// Inputs:
+//  command = the number of the command to send
+//  buffer = pointer to bytes of additional data for the command
+//  size = the size of the buffer
+//
+// Returns:
+//  0 on success, any negative number is an error code
+//
+extern short sdc_ioctrl_n(short command, unsigned char * buffer, short size);
+
+/* Disk Status Bits (DSTATUS) */
+
+// FatFS original Naming
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+#define STA_PROTECT		0x04	/* Write protected */
+
+// Gen X Implementation
+#define SDC_SECTOR_SIZE         512         // Size of a block on the SDC
+#define SDC_STAT_NOINIT         0x01        // SD has not been initialized
+#define SDC_STAT_PRESENT        0x02        // SD is present
+#define SDC_STAT_PROTECTED      0x04        // SD is write-protected
+
+
+/* Command code for disk_ioctrl fucntion */
+
+/* Generic command (Used by FatFs) */
+#define CTRL_SYNC			0	/* Complete pending write process (needed at FF_FS_READONLY == 0) */
+#define GET_SECTOR_COUNT	1	/* Get media size (needed at FF_USE_MKFS == 1) */
+#define GET_SECTOR_SIZE		2	/* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
+#define GET_BLOCK_SIZE		3	/* Get erase block size (needed at FF_USE_MKFS == 1) */
+#define CTRL_TRIM			4	/* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
+
+/* Generic command (Not used by FatFs) */
+#define CTRL_POWER			5	/* Get/Set power status */
+#define CTRL_LOCK			6	/* Lock/Unlock media removal */
+#define CTRL_EJECT			7	/* Eject media */
+#define CTRL_FORMAT			8	/* Create physical format on the media */
+
+/* MMC/SDC specific ioctl command */
+#define MMC_GET_TYPE		10	/* Get card type */
+#define MMC_GET_CSD			11	/* Get CSD */
+#define MMC_GET_CID			12	/* Get CID */
+#define MMC_GET_OCR			13	/* Get OCR */
+#define MMC_GET_SDSTAT		14	/* Get SD status */
+#define ISDIO_READ			55	/* Read data form SD iSDIO register */
+#define ISDIO_WRITE			56	/* Write data to SD iSDIO register */
+#define ISDIO_MRITE			57	/* Masked write data to SD iSDIO register */
+
+/* ATA/CF specific ioctl command */
+#define ATA_GET_REV			20	/* Get F/W revision */
+#define ATA_GET_MODEL		21	/* Get model name */
+#define ATA_GET_SN			22	/* Get serial number */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

src/dev/superio.c

@@ -5,19 +5,16 @@
 
 #if HAS_SUPERIO
 
-static void configure_zones(void);
-
 /*
  * Initialize the SuperIO registers
  */
-void superio_init(void) {
+ void superio_init(void) {
-#if MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_GENX
+
-    // This initialization used to be done by the FPGA.
+  //unsigned int i;
-    // Other machines A2560K/C256FMX will have this change soon to.
+   //configure_zones(); // This Init used to be done by the FPGA.
-    configure_zones(); 
+  //for (i = 0; i < 2000000; i++);
-#endif
+   
-     
+	 *GP10_REG = 0x01;
-    *GP10_REG = 0x01;
     *GP11_REG = 0x01;
     *GP12_REG = 0x01;
     *GP13_REG = 0x01;
@@ -26,51 +23,51 @@ void superio_init(void) {
     *GP16_REG = 0x05;
     *GP17_REG = 0x05;
 
-    *GP20_REG = 0x00;
+ 	*GP20_REG = 0x00;
-    *GP24_REG = 0x01;
+ 	*GP24_REG = 0x01;
-    *GP25_REG = 0x05;
+ 	*GP25_REG = 0x05;
-    *GP26_REG = 0x84;
+ 	*GP26_REG = 0x84;
 
-    *GP30_REG = 0x01;
+ 	*GP30_REG = 0x01;
-    *GP31_REG = 0x01;
+ 	*GP31_REG = 0x01;
-    *GP32_REG = 0x01;
+ 	*GP32_REG = 0x01;
-    *GP33_REG = 0x04; // FAN1 GPIO Config
+ 	*GP33_REG = 0x04; // FAN1 GPIO Config
-    *GP34_REG = 0x01;
+ 	*GP34_REG = 0x01;
-    *GP35_REG = 0x01;
+ 	*GP35_REG = 0x01;
-    *GP36_REG = 0x01;
+ 	*GP36_REG = 0x01;
-    *GP37_REG = 0x01;
+ 	*GP37_REG = 0x01;
 
-    *GP42_REG = 0x01;
+ 	*GP42_REG = 0x01;
-    *GP43_REG = 0x01;
+ 	*GP43_REG = 0x01;
 
-    *GP50_REG = 0x05;
+ 	*GP50_REG = 0x05;
-    *GP51_REG = 0x05;
+ 	*GP51_REG = 0x05;
-    *GP52_REG = 0x05;
+ 	*GP52_REG = 0x05;
-    *GP53_REG = 0x04;
+ 	*GP53_REG = 0x04;
-    *GP54_REG = 0x05;
+ 	*GP54_REG = 0x05;
-    *GP55_REG = 0x04;
+ 	*GP55_REG = 0x04;
-    *GP56_REG = 0x05;
+ 	*GP56_REG = 0x05;
-    *GP57_REG = 0x04;
+ 	*GP57_REG = 0x04;
 
-    *GP60_REG = 0x84;
+ 	*GP60_REG = 0x84;
-    *GP61_REG = 0x84;
+ 	*GP61_REG = 0x84;
 
-    *GP1_REG = 0x00;
+ 	*GP1_REG = 0x00;
-    *GP2_REG = 0x01;
+ 	*GP2_REG = 0x01;
-    *GP3_REG = 0x00;
+ 	*GP3_REG = 0x00;
-    *GP4_REG = 0x00;
+ 	*GP4_REG = 0x00;
-    *GP5_REG = 0x00;
+ 	*GP5_REG = 0x00;
-    *GP6_REG = 0x00;
+ 	*GP6_REG = 0x00;
 
-    *LED1_REG = 0x01;
+ 	*LED1_REG = 0x01;
-    *LED2_REG = 0x02;
+ 	*LED2_REG = 0x02;
 
     *FAN1_REG = 0xE0;       // <= Value to change to Get the Fan running.
                             // See doc for more options, need to set $80 to get it started and use other bits to change the PWN...
     *FAN_CTRL_REG = 0x01;
-}
+ }
 
-static void configure_zones(void) {
+void configure_zones(void) {
     // First step is to get into the Configuration Mode
     *CONFIG_0x2E_REG = 0x55;    // We need to Get into the Config Mode with 0x55
 
@@ -131,7 +128,7 @@ static void configure_zones(void) {
     *CONFIG_0x2E_REG = 0x30;
     *CONFIG_0x2F_REG = 0x01;
 
-    // Setting Up Device 5 - Serial Port 2 
+     // Setting Up Device 5 - Serial Port 2 
     // {8'h03,16'h02F8,8'h05};
     // LD
     *CONFIG_0x2E_REG = 0x07;
@@ -149,7 +146,7 @@ static void configure_zones(void) {
     *CONFIG_0x2E_REG = 0x30;
     *CONFIG_0x2F_REG = 0x01;  
 
-    // Setting Up Device 7 - Keyboard 
+     // Setting Up Device 7 - Keyboard 
     // {8'h01, 16'h0060,8'h07};
     // LD
     *CONFIG_0x2E_REG = 0x07;
@@ -170,7 +167,7 @@ static void configure_zones(void) {
     *CONFIG_0x2E_REG = 0x30;
     *CONFIG_0x2F_REG = 0x01;
 
-    // Setting Up Device 9 - Game Port
+      // Setting Up Device 9 - Game Port
     // {8'h00, 16'h0200,8'h09};
     // LD
     *CONFIG_0x2E_REG = 0x07;
@@ -188,7 +185,7 @@ static void configure_zones(void) {
     *CONFIG_0x2E_REG = 0x30;
     *CONFIG_0x2F_REG = 0x01;
 
-    // Setting Up Device 10 - PME (Power Management)
+      // Setting Up Device 10 - PME (Power Management)
     // {8'h00, 16'h0100,8'h0A};
     // LD
     *CONFIG_0x2E_REG = 0x07;
@@ -225,7 +222,7 @@ static void configure_zones(void) {
     *CONFIG_0x2F_REG = 0x01;
 
     // Supplemental Settings
-    // Power On Device 
+     // Power On Device 
     *CONFIG_0x2E_REG = 0x22;
     *CONFIG_0x2F_REG = 0xFF;   
     // We are done with config. 
@@ -233,5 +230,19 @@ static void configure_zones(void) {
 
     *GP60_REG = 0x84;           // THis is to replicate the FPGA behavior when it did the config.
     *LED1_REG = 0x01;           // THis is to replace the FPGA behavior when it did the config in hardware.
+ }
+
+void UnReset_LPC( ) {
+  unsigned int i;
+  *GABE_CTRL_LPC = *GABE_CTRL_LPC | 0x100; // This will set the LPC_RSTn which is its normal operation state.
+  for (i = 0; i< 1000; i++);
+
+  *GABE_CTRL_LPC = *GABE_CTRL_LPC & 0xFEFF; // This will set the LPC_RSTn which is its normal operation state.
+  for (i = 0; i< 400000; i++); 
+  // So let's Unreset it
+  *GABE_CTRL_LPC = *GABE_CTRL_LPC | 0x100; // This will set the LPC_RSTn which is its normal operation state.
+  // Now, let's pause a bit before configuration time
+  for (i = 0; i< 2000000; i++);
 }
+
 #endif

src/dev/txt_screen.c

@@ -685,14 +685,12 @@ void txt_delete(short screen, short count) {
     t_rect old_region, region;
     short left;
 
-   	TRACE2("txt_delete(%d,%d)", screen, (int)count);
+   	TRACE2("txt_delete(%d,%d)", screen, count);
 	
     if (count > 0) {
         txt_get_xy(screen, &cursor);
         txt_get_region(screen, &old_region);
 
-TRACE4("Got region %d,%d,%d,%d", (int)old_region.origin.x, (int)old_region.origin.y, (int)old_region.size.width, (int)old_region.size.height);
-
         if (count > cursor.x) {
             count = cursor.x;
         }
@@ -701,8 +699,6 @@ TRACE4("Got region %d,%d,%d,%d", (int)old_region.origin.x, (int)old_region.origi
         region.origin.y = old_region.origin.y + cursor.y;
         region.size.width = old_region.size.width - cursor.x;
         region.size.height = 1;
-
-        TRACE4("Setting region %d,%d,%d,%d", (int)region.origin.x, (int)region.origin.y, (int)region.size.width, (int)region.size.height);
         txt_set_region(screen, &region);
         txt_scroll(screen, count, 0);
         txt_set_region(screen, &old_region);

src/dev/txt_screen.h

@@ -9,13 +9,14 @@
 
 #include "types.h"
 
-#define TXT_CNT_SCREENS 5       /**< The maximum number of screens supported */
+#define TXT_CNT_SCREENS 2       /**< The maximum number of screens supported */
 
 #define TXT_MODE_TEXT   0x0001  /**< The bit to enable text mode */
 #define TXT_MODE_BITMAP 0x0002  /**< The bit to enable bitmap graphics mode */
 #define TXT_MODE_SPRITE 0x0004  /**< The bit to enable sprite graphics mode */
 #define TXT_MODE_TILE   0x0008  /**< The bit to enable tile graphics mode */
 #define TXT_MODE_SLEEP  0x0010  /**< The bit to put the monitor to sleep by disabling sync */
+#define VID_SLEEP_GENX  0x0080  /**< The bit to put the monitor to sleep by disabling sync */
 
 /**
  * @struct s_txt_capabilities

src/dev/uart.c

@@ -80,13 +80,13 @@ void uart_init(short uart) {
 
     if (uart_base) {
         /* Default to 9600 bps */
-        uart_setbps(uart, UART_9600);
+        uart_setbps(uart, UART_115200);
 
         /* Set: no parity, 1 stop bit, 8 data bits */
         uart_setlcr(uart,  LCR_PARITY_NONE | LCR_STOPBIT_1 | LCR_DATABITS_8);
 
         /* Enable FIFO, set for 56 byte trigger level */
-        uart_base[UART_FCR] = 0xC1;
+       uart_base[UART_FCR] = 0xC1;
     }
 }
 
@@ -134,17 +134,19 @@ short uart_can_send(short uart) {
  */
 void uart_put(short uart, unsigned char b) {
     volatile unsigned char * uart_base = uart_get_base(uart);
+    unsigned char status = 0;   
+    unsigned char Timeout = 64;
 
     if (uart_base) {
-        unsigned char status = 0;
-
         /* Wait for the transmit buffer to be empty */
         do {
             status = uart_base[UART_LSR];
-        } while ((status & LSR_XMIT_EMPTY) == 0);
+            Timeout = Timeout - 1;
+        } while (((status & LSR_XMIT_EMPTY) == 0) && Timeout);
 
         /* Send the byte */
         uart_base[UART_TRHB] = b;
+        //uart_base[UART_TRHB] = 0x55;
     }
 }
 

src/fatfs/c256_diskio.c

@@ -81,7 +81,7 @@ DRESULT disk_read (
 				logmsg(LOG_ERROR, "disk changed.");
 				return RES_NOTRDY;
 			} else {
-				logmsg(LOG_ERROR, "gerneral error");
+				logmsg(LOG_ERROR, "General error");
 				return RES_PARERR;
 			}
 		} else {

src/foenixmcp.c

@@ -4,7 +4,7 @@
 
 #include "log_level.h"
 #ifndef DEFAULT_LOG_LEVEL
-    #define DEFAULT_LOG_LEVEL LOG_TRACE
+    #define DEFAULT_LOG_LEVEL LOG_VERBOSE
 #endif
 
 #include <stdio.h>
@@ -95,7 +95,7 @@ int main(int argc, char * argv[]) {
         INFO("CLI initialized.");
     }
 	
-#if MODEL == MODEL_FOENIX_A2560U || MODEL == MODEL_FOENIX_A2560U_PLUS || MODEL == MODEL_FOENIX_A2560X
+#if MODEL == MODEL_FOENIX_A2560U || MODEL == MODEL_FOENIX_A2560U_PLUS || MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_A2560K
     // Make sure the command path is set to the default before we get started
     cli_command_set("");
 TRACE("Calling boot_screen()");
@@ -156,28 +156,15 @@ static void hw_initialize(void) {
 	 * functional (e.g. if debugging to the serial port) so it may call uart_init. */
 
 #if HAS_SUPERIO
-    /* Initialize the SuperIO chip. We do this early so to have the UARTs available for debug output */
+    UnReset_LPC();      // Bit[8] of GABE Control Register is Controlling the RESET
+    configure_zones(); // This Init used to be done by the FPGA.    
     superio_init();
-    INFO("SuperIO initialized");
 #endif
-    log_init();
 
+    log_init();
 	/* Fill out the system information */
 	sys_get_information(&info);
 
-    #if 0
-    char msg[] = "This is some text to test that the debug to UART works ok\r\n";
-    {
-        char *c = (char*)msg;
-        while (*c) {
-            uart_put(1, *c++);
-        }
-    }
-
-    // The text below gets corrupted. VBCC libc's not being properly initialized if we didn't call ___main ?
-    //DEBUG("This is some text to test that the debug to UART works ok");
-    #endif
-
     /* Initialize the memory system.
      * TODO: The amount of RAM should depend on the machine! E.g; U only has 2MB. */
     mem_init(0x3d0000);
@@ -212,9 +199,10 @@ static void hw_initialize(void) {
 
     /* Initialize the CODEC (mixer chip) */
     init_codec();
+    INFO("CODEC initialized");
 
 	/* PS/2 keyboard and mouse */
-    if ((res = ps2_init())) {
+    if ((res = ps2_init())) {        
         ERROR1("FAILED: PS/2 keyboard initialization (%d)", res);
     } else {
         INFO("PS/2 keyboard initialized.");
@@ -326,7 +314,7 @@ static void os_devices_initialize(void) {
         INFO("PATA driver installed.");
     }
 
-    if ((res = sdc_install())) {
+    if ((res = sdc_install_n())) {
         ERROR1("FAILED: SDC driver installation (%d)", res);
     } else {
         INFO("SDC driver installed.");

src/include/A2560K/ps2_a2560k.h

@@ -5,10 +5,10 @@
  * Ports for the PS/2 keyboard and mouse on the A2560K
  */
 
-#define PS2_STATUS      ((unsigned char *)0xFEC02064)
+#define PS2_STATUS      ((volatile uint8_t *)0xFEC02064)
-#define PS2_CMD_BUF     ((unsigned char *)0xFEC02064)
+#define PS2_CMD_BUF     ((volatile uint8_t *)0xFEC02064)
-#define PS2_OUT_BUF     ((unsigned char *)0xFEC02060)
+#define PS2_OUT_BUF     ((volatile uint8_t *)0xFEC02060)
-#define PS2_INPT_BUF    ((unsigned char *)0xFEC02060)
+#define PS2_INPT_BUF    ((volatile uint8_t *)0xFEC02060)
-#define PS2_DATA_BUF    ((unsigned char *)0xFEC02060)
+#define PS2_DATA_BUF    ((volatile uint8_t *)0xFEC02060)
 
 #endif

src/include/A2560K/sdc_a2560k.h

@@ -13,27 +13,27 @@
 #define GABE_DIP_USER_0         0x00000100      /* DIP switch: User 0 */
 #define GABE_DIP_USER_1         0x00000200      /* DIP switch: User 1 */
 
-#define SDC_VERSION_REG         ((unsigned char *)0xFEC00300)
+//#define SDC_VERSION_REG         ((unsigned char *)0xFEC00300)
-#define SDC_CONTROL_REG         ((unsigned char *)0xFEC00301)
+//#define SDC_CONTROL_REG         ((unsigned char *)0xFEC00301)
-#define SDC_TRANS_TYPE_REG      ((unsigned char *)0xFEC00302)
+//#define SDC_TRANS_TYPE_REG      ((unsigned char *)0xFEC00302)
 
-#define SDC_TRANS_CONTROL_REG   ((unsigned char *)0xFEC00303)
+//#define SDC_TRANS_CONTROL_REG   ((unsigned char *)0xFEC00303)
-#define SDC_TRANS_STATUS_REG    ((unsigned char *)0xFEC00304)
+//#define SDC_TRANS_STATUS_REG    ((unsigned char *)0xFEC00304)
-#define SDC_TRANS_ERROR_REG     ((unsigned char *)0xFEC00305)
+//#define SDC_TRANS_ERROR_REG     ((unsigned char *)0xFEC00305)
-#define SDC_DIRECT_ACCESS_REG   ((unsigned char *)0xFEC00306)
+//#define SDC_DIRECT_ACCESS_REG   ((unsigned char *)0xFEC00306)
-#define SDC_SD_ADDR_7_0_REG     ((unsigned char *)0xFEC00307)
+//#define SDC_SD_ADDR_7_0_REG     ((unsigned char *)0xFEC00307)
-#define SDC_SD_ADDR_15_8_REG    ((unsigned char *)0xFEC00308)
+//#define SDC_SD_ADDR_15_8_REG    ((unsigned char *)0xFEC00308)
-#define SDC_SD_ADDR_23_16_REG   ((unsigned char *)0xFEC00309)
+//#define SDC_SD_ADDR_23_16_REG   ((unsigned char *)0xFEC00309)
-#define SDC_SD_ADDR_31_24_REG   ((unsigned char *)0xFEC0030A)
+//#define SDC_SD_ADDR_31_24_REG   ((unsigned char *)0xFEC0030A)
 
-#define SDC_SPI_CLK_DEL_REG     ((unsigned char *)0xFEC0030B)
+//#define SDC_SPI_CLK_DEL_REG     ((unsigned char *)0xFEC0030B)
 
-#define SDC_RX_FIFO_DATA_REG    ((unsigned char *)0xFEC00310)
+//#define SDC_RX_FIFO_DATA_REG    ((unsigned char *)0xFEC00310)
-#define SDC_RX_FIFO_DATA_CNT_HI ((unsigned char *)0xFEC00312)
+//#define SDC_RX_FIFO_DATA_CNT_HI ((unsigned char *)0xFEC00312)
-#define SDC_RX_FIFO_DATA_CNT_LO ((unsigned char *)0xFEC00313)
+//#define SDC_RX_FIFO_DATA_CNT_LO ((unsigned char *)0xFEC00313)
-#define SDC_RX_FIFO_CTRL_REG    ((unsigned char *)0xFEC00314)
+//#define SDC_RX_FIFO_CTRL_REG    ((unsigned char *)0xFEC00314)
 
-#define SDC_TX_FIFO_DATA_REG    ((unsigned char *)0xFEC00320)
+//#define SDC_TX_FIFO_DATA_REG    ((unsigned char *)0xFEC00320)
-#define SDC_TX_FIFO_CTRL_REG    ((unsigned char *)0xFEC00324)
+//#define SDC_TX_FIFO_CTRL_REG    ((unsigned char *)0xFEC00324)
 
 #endif

src/include/features.h

@@ -70,4 +70,4 @@
     #define HAS_SNES_GAMEPAD 0
 #endif
 
-#endif
+#endif

src/include/superio.h

@@ -13,8 +13,11 @@
 
 #define SUPERIO_BASE (0xFEC02000)
 
- void superio_init(void);
+void superio_init(void);
+void configure_zones(void);
+void UnReset_LPC(void);
 
+#define GABE_CTRL_LPC   ((volatile uint32_t *)0xFEC00000)
 
 #define CONFIG_0x2E_REG ((volatile uint8_t *)0xFEC0202E)
 #define CONFIG_0x2F_REG ((volatile uint8_t *)0xFEC0202F)

src/log.h

@@ -26,7 +26,8 @@
 #ifndef LOG_CHANNEL
   // If the device has a second screen, we default to logging to it
   #if MODEL == MODEL_FOENIX_A2560K || MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_GENX
-    #define LOG_CHANNEL LOG_CHANNEL_CHANNEL_A_LOW_LEVEL
+    //#define LOG_CHANNEL LOG_CHANNEL_CHANNEL_A
+    #define LOG_CHANNEL LOG_CHANNEL_CHANNEL_A    
   #else
     #define LOG_CHANNEL LOG_CHANNEL_COM1
   #endif

src/proc.c

@@ -37,8 +37,8 @@ extern void call_user(long start, long stack, int argc, char * argv[]);
 void proc_exec(long start, long stack, int argc, char * argv[]) {
     TRACE("proc_exec");
 
-    INFO1(LOG_INFO, "proc_exec start: %d");
+    //INFO1(LOG_INFO, "proc_exec start: %d");
-    INFO1(LOG_INFO, "proc_exec stack: %d");
+    //INFO1(LOG_INFO, "proc_exec stack: %d");
 
     g_proc_result = 0;
     call_user(start, stack, argc, argv);

src/version.h

@@ -6,7 +6,7 @@
 #define __VERSION_H
 
 #define VER_MAJOR 1
-#define VER_MINOR 3
+#define VER_MINOR 4
-#define VER_BUILD 1
+#define VER_BUILD 11
 
 #endif

vbcc/targets/m68k-foenix/vlink_flash_a2560x.cmd

@@ -8,7 +8,7 @@ STACK_LEN = 0x400;
 VECTOR_LEN = 0x1000;
 STORE_LEN = 0x00030000;
 KERNEL_LEN = 0x000a0000;
-FLASH_LEN = 0x00200000;
+FLASH_LEN = 0x00400000;
 PAGE_SIZE = 0x00010000;
 
 MEMORY

vbcc/targets/m68k-foenix/vlink_ram_a2560x.cmd

@@ -1,14 +1,14 @@
 BINFILE_START = 0x00000000;
 FLASH_START = 0xFFC10000;
 VECTOR_START = 0x00000000;
-STORE_START = 0x00180000;
+STORE_START = 0x00280000;
-KERNEL_START = 0x001C0000;
+KERNEL_START = 0x00300000;
 
 STACK_LEN = 0x400;
 VECTOR_LEN = 0x400;
 STORE_LEN = 0x00030000;
 KERNEL_LEN = 0x000a0000;
-FLASH_LEN = 0x00200000;
+FLASH_LEN = 0x00400000;
 PAGE_SIZE = 0x00010000;
 
 MEMORY