From 4707637b5877f8dc6dde2ea93975c449a8885943 Mon Sep 17 00:00:00 2001 From: Vincent Barrilliot Date: Fri, 8 Dec 2023 12:29:49 +0100 Subject: [PATCH] Fix indentation --- src/dev/superio.c | 88 +++++++++++++++++++++++------------------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/src/dev/superio.c b/src/dev/superio.c index 17a26a1..b0fbcac 100644 --- a/src/dev/superio.c +++ b/src/dev/superio.c @@ -10,14 +10,14 @@ static void configure_zones(void); /* * Initialize the SuperIO registers */ - void superio_init(void) { +void superio_init(void) { #if MODEL == MODEL_FOENIX_A2560X || MODEL == MODEL_FOENIX_GENX - // This initialization used to be done by the FPGA. - // Other machines A2560K/C256FMX will have this change soon to. - configure_zones(); + // This initialization used to be done by the FPGA. + // Other machines A2560K/C256FMX will have this change soon to. + configure_zones(); #endif - *GP10_REG = 0x01; + *GP10_REG = 0x01; *GP11_REG = 0x01; *GP12_REG = 0x01; *GP13_REG = 0x01; @@ -26,49 +26,49 @@ static void configure_zones(void); *GP16_REG = 0x05; *GP17_REG = 0x05; - *GP20_REG = 0x00; - *GP24_REG = 0x01; - *GP25_REG = 0x05; - *GP26_REG = 0x84; + *GP20_REG = 0x00; + *GP24_REG = 0x01; + *GP25_REG = 0x05; + *GP26_REG = 0x84; - *GP30_REG = 0x01; - *GP31_REG = 0x01; - *GP32_REG = 0x01; - *GP33_REG = 0x04; // FAN1 GPIO Config - *GP34_REG = 0x01; - *GP35_REG = 0x01; - *GP36_REG = 0x01; - *GP37_REG = 0x01; + *GP30_REG = 0x01; + *GP31_REG = 0x01; + *GP32_REG = 0x01; + *GP33_REG = 0x04; // FAN1 GPIO Config + *GP34_REG = 0x01; + *GP35_REG = 0x01; + *GP36_REG = 0x01; + *GP37_REG = 0x01; - *GP42_REG = 0x01; - *GP43_REG = 0x01; + *GP42_REG = 0x01; + *GP43_REG = 0x01; - *GP50_REG = 0x05; - *GP51_REG = 0x05; - *GP52_REG = 0x05; - *GP53_REG = 0x04; - *GP54_REG = 0x05; - *GP55_REG = 0x04; - *GP56_REG = 0x05; - *GP57_REG = 0x04; + *GP50_REG = 0x05; + *GP51_REG = 0x05; + *GP52_REG = 0x05; + *GP53_REG = 0x04; + *GP54_REG = 0x05; + *GP55_REG = 0x04; + *GP56_REG = 0x05; + *GP57_REG = 0x04; - *GP60_REG = 0x84; - *GP61_REG = 0x84; + *GP60_REG = 0x84; + *GP61_REG = 0x84; - *GP1_REG = 0x00; - *GP2_REG = 0x01; - *GP3_REG = 0x00; - *GP4_REG = 0x00; - *GP5_REG = 0x00; - *GP6_REG = 0x00; + *GP1_REG = 0x00; + *GP2_REG = 0x01; + *GP3_REG = 0x00; + *GP4_REG = 0x00; + *GP5_REG = 0x00; + *GP6_REG = 0x00; - *LED1_REG = 0x01; - *LED2_REG = 0x02; + *LED1_REG = 0x01; + *LED2_REG = 0x02; *FAN1_REG = 0xE0; // <= Value to change to Get the Fan running. // See doc for more options, need to set $80 to get it started and use other bits to change the PWN... *FAN_CTRL_REG = 0x01; - } +} static void configure_zones(void) { // First step is to get into the Configuration Mode @@ -131,7 +131,7 @@ static void configure_zones(void) { *CONFIG_0x2E_REG = 0x30; *CONFIG_0x2F_REG = 0x01; - // Setting Up Device 5 - Serial Port 2 + // Setting Up Device 5 - Serial Port 2 // {8'h03,16'h02F8,8'h05}; // LD *CONFIG_0x2E_REG = 0x07; @@ -149,7 +149,7 @@ static void configure_zones(void) { *CONFIG_0x2E_REG = 0x30; *CONFIG_0x2F_REG = 0x01; - // Setting Up Device 7 - Keyboard + // Setting Up Device 7 - Keyboard // {8'h01, 16'h0060,8'h07}; // LD *CONFIG_0x2E_REG = 0x07; @@ -170,7 +170,7 @@ static void configure_zones(void) { *CONFIG_0x2E_REG = 0x30; *CONFIG_0x2F_REG = 0x01; - // Setting Up Device 9 - Game Port + // Setting Up Device 9 - Game Port // {8'h00, 16'h0200,8'h09}; // LD *CONFIG_0x2E_REG = 0x07; @@ -188,7 +188,7 @@ static void configure_zones(void) { *CONFIG_0x2E_REG = 0x30; *CONFIG_0x2F_REG = 0x01; - // Setting Up Device 10 - PME (Power Management) + // Setting Up Device 10 - PME (Power Management) // {8'h00, 16'h0100,8'h0A}; // LD *CONFIG_0x2E_REG = 0x07; @@ -225,7 +225,7 @@ static void configure_zones(void) { *CONFIG_0x2F_REG = 0x01; // Supplemental Settings - // Power On Device + // Power On Device *CONFIG_0x2E_REG = 0x22; *CONFIG_0x2F_REG = 0xFF; // We are done with config. @@ -233,5 +233,5 @@ static void configure_zones(void) { *GP60_REG = 0x84; // THis is to replicate the FPGA behavior when it did the config. *LED1_REG = 0x01; // THis is to replace the FPGA behavior when it did the config in hardware. - } +} #endif